Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7419111 [patent_doc_number] => 20040177329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method' [patent_app_type] => new [patent_app_number] => 10/484231 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177329.pdf [firstpage_image] =>[orig_patent_app_number] => 10484231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/484231
Method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters, and an integrated circuit design and an integrated circuit produced by applying such method Jun 30, 2002 Issued
Array ( [id] => 7447045 [patent_doc_number] => 20040003361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Dynamically reconfiguring clock domains on a chip' [patent_app_type] => new [patent_app_number] => 10/184545 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5404 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003361.pdf [firstpage_image] =>[orig_patent_app_number] => 10184545 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184545
Dynamically reconfiguring clock domains on a chip Jun 27, 2002 Issued
Array ( [id] => 736512 [patent_doc_number] => 07043711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'System and method for defining semiconductor device layout parameters' [patent_app_type] => utility [patent_app_number] => 10/183911 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3340 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/043/07043711.pdf [firstpage_image] =>[orig_patent_app_number] => 10183911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183911
System and method for defining semiconductor device layout parameters Jun 25, 2002 Issued
Array ( [id] => 1170516 [patent_doc_number] => 06763513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Clock tree synthesizer for balancing reconvergent and crossover clock trees' [patent_app_type] => B1 [patent_app_number] => 10/183331 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5295 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763513.pdf [firstpage_image] =>[orig_patent_app_number] => 10183331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183331
Clock tree synthesizer for balancing reconvergent and crossover clock trees Jun 25, 2002 Issued
Array ( [id] => 1139578 [patent_doc_number] => 06789248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization' [patent_app_type] => B1 [patent_app_number] => 10/178401 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8056 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789248.pdf [firstpage_image] =>[orig_patent_app_number] => 10178401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/178401
Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization Jun 23, 2002 Issued
Array ( [id] => 984845 [patent_doc_number] => 06928632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method of designing semiconductor device using power supply bump connections' [patent_app_type] => utility [patent_app_number] => 10/175001 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 13266 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928632.pdf [firstpage_image] =>[orig_patent_app_number] => 10175001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175001
Method of designing semiconductor device using power supply bump connections Jun 19, 2002 Issued
Array ( [id] => 937754 [patent_doc_number] => 06976237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and apparatus for estimating distances in a region' [patent_app_type] => utility [patent_app_number] => 10/174661 [patent_app_country] => US [patent_app_date] => 2002-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 8703 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976237.pdf [firstpage_image] =>[orig_patent_app_number] => 10174661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174661
Method and apparatus for estimating distances in a region Jun 18, 2002 Issued
Array ( [id] => 1071079 [patent_doc_number] => 06845496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Semiconductor integrated circuit device using programmable peripheral control' [patent_app_type] => utility [patent_app_number] => 10/173661 [patent_app_country] => US [patent_app_date] => 2002-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2975 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845496.pdf [firstpage_image] =>[orig_patent_app_number] => 10173661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173661
Semiconductor integrated circuit device using programmable peripheral control Jun 18, 2002 Issued
Array ( [id] => 6798582 [patent_doc_number] => 20030177457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Optimization of digital designs' [patent_app_type] => new [patent_app_number] => 10/172746 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17380 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177457.pdf [firstpage_image] =>[orig_patent_app_number] => 10172746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172746
Optimization of digital designs Jun 13, 2002 Issued
Array ( [id] => 1167276 [patent_doc_number] => 06772405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Insertable block tile for interconnecting to a device embedded in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/172431 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3511 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772405.pdf [firstpage_image] =>[orig_patent_app_number] => 10172431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172431
Insertable block tile for interconnecting to a device embedded in an integrated circuit Jun 12, 2002 Issued
Array ( [id] => 7626787 [patent_doc_number] => 06807658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Systems and methods for performing clock gating checks' [patent_app_type] => B2 [patent_app_number] => 10/163391 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6164 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807658.pdf [firstpage_image] =>[orig_patent_app_number] => 10163391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163391
Systems and methods for performing clock gating checks Jun 4, 2002 Issued
Array ( [id] => 6265792 [patent_doc_number] => 20020188922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method for storing multiple levels of design data in a common database' [patent_app_type] => new [patent_app_number] => 10/159531 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4949 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188922.pdf [firstpage_image] =>[orig_patent_app_number] => 10159531 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159531
Method for storing multiple levels of design data in a common database May 30, 2002 Abandoned
Array ( [id] => 1097554 [patent_doc_number] => 06826733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Parameter variation tolerant method for circuit design optimization' [patent_app_type] => B2 [patent_app_number] => 10/159921 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826733.pdf [firstpage_image] =>[orig_patent_app_number] => 10159921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159921
Parameter variation tolerant method for circuit design optimization May 29, 2002 Issued
Array ( [id] => 1001852 [patent_doc_number] => 06912698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Skew lots for IC oscillators and other analog circuits' [patent_app_type] => utility [patent_app_number] => 10/155301 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3072 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912698.pdf [firstpage_image] =>[orig_patent_app_number] => 10155301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155301
Skew lots for IC oscillators and other analog circuits May 22, 2002 Issued
Array ( [id] => 753573 [patent_doc_number] => 07028284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Convergence technique for model-based optical and process correction' [patent_app_type] => utility [patent_app_number] => 10/147280 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4893 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028284.pdf [firstpage_image] =>[orig_patent_app_number] => 10147280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/147280
Convergence technique for model-based optical and process correction May 14, 2002 Issued
Array ( [id] => 7042855 [patent_doc_number] => 20050160402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method and apparatus for adding advanced instructions in an extensible processor architecture' [patent_app_type] => utility [patent_app_number] => 10/146655 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11392 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160402.pdf [firstpage_image] =>[orig_patent_app_number] => 10146655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146655
Method and apparatus for adding advanced instructions in an extensible processor architecture May 12, 2002 Issued
Array ( [id] => 1192742 [patent_doc_number] => 06735750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'System and method for correcting charge collector violations' [patent_app_type] => B2 [patent_app_number] => 10/144072 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735750.pdf [firstpage_image] =>[orig_patent_app_number] => 10144072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144072
System and method for correcting charge collector violations May 12, 2002 Issued
Array ( [id] => 6844608 [patent_doc_number] => 20030149955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Rule-based opc evaluating method and simulation base opc model evaluating method' [patent_app_type] => new [patent_app_number] => 10/332631 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149955.pdf [firstpage_image] =>[orig_patent_app_number] => 10332631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/332631
Rule based OPC evaluating method and simulation-based OPC model evaluating method May 9, 2002 Issued
Array ( [id] => 7613764 [patent_doc_number] => 06898767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method and apparatus for custom design in a standard cell design environment' [patent_app_type] => utility [patent_app_number] => 10/144101 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898767.pdf [firstpage_image] =>[orig_patent_app_number] => 10144101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144101
Method and apparatus for custom design in a standard cell design environment May 8, 2002 Issued
Array ( [id] => 943747 [patent_doc_number] => 06971080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Placement based design cells injection into an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/135941 [patent_app_country] => US [patent_app_date] => 2002-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3337 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/971/06971080.pdf [firstpage_image] =>[orig_patent_app_number] => 10135941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135941
Placement based design cells injection into an integrated circuit design Apr 28, 2002 Issued
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