Jeffrey T. Knapp

Array ( [id] => 6389672 [patent_doc_number] => 20020120913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Computer readable storage medium' [patent_app_type] => new [patent_app_number] => 10/133574 [patent_app_country] => US [patent_app_date] => 2002-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6939 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120913.pdf [firstpage_image] =>[orig_patent_app_number] => 10133574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6256226 [patent_doc_number] => 20020186246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Interactive loop configuration in a behavioral synthesis tool' [patent_app_type] => new [patent_app_number] => 10/126911 [patent_app_country] => US [patent_app_date] => 2002-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4445 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186246.pdf [firstpage_image] =>[orig_patent_app_number] => 10126911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1110042 [patent_doc_number] => 06813753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of determining library parameters using timing surface planarity' [patent_app_type] => B2 [patent_app_number] => 10/124021 [patent_app_country] => US [patent_app_date] => 2002-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 9834 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813753.pdf [firstpage_image] =>[orig_patent_app_number] => 10124021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1170766 [patent_doc_number] => 06766507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Mask/wafer control structure and algorithm for placement' [patent_app_type] => B2 [patent_app_number] => 10/121811 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1944 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766507.pdf [firstpage_image] =>[orig_patent_app_number] => 10121811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 758111 [patent_doc_number] => 07024641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Integrated circuit having a programmable gate array and a field programmable gate array and methods of designing and manufacturing the same using testing IC before configuring FPGA' [patent_app_type] => utility [patent_app_number] => 10/119821 [patent_app_country] => US [patent_app_date] => 2002-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3760 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024641.pdf [firstpage_image] =>[orig_patent_app_number] => 10119821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6265803 [patent_doc_number] => 20020188925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Pattern-creating method, pattern-processing apparatus and exposure mask' [patent_app_type] => new [patent_app_number] => 10/117091 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9653 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188925.pdf [firstpage_image] =>[orig_patent_app_number] => 10117091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6154673 [patent_doc_number] => 20020145444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign' [patent_app_type] => new [patent_app_number] => 10/114038 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10074 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145444.pdf [firstpage_image] =>[orig_patent_app_number] => 10114038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1049760 [patent_doc_number] => 06865726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'IC layout system employing a hierarchical database by updating cell library' [patent_app_type] => utility [patent_app_number] => 10/117761 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 10169 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/865/06865726.pdf [firstpage_image] =>[orig_patent_app_number] => 10117761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7618349 [patent_doc_number] => 06944844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'System and method to determine impact of line end shortening' [patent_app_type] => utility [patent_app_number] => 10/116661 [patent_app_country] => US [patent_app_date] => 2002-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3078 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944844.pdf [firstpage_image] =>[orig_patent_app_number] => 10116661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6556785 [patent_doc_number] => 20020194574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Method for laying out electronic circuit and program thereof' [patent_app_type] => new [patent_app_number] => 10/112703 [patent_app_country] => US [patent_app_date] => 2002-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2486 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194574.pdf [firstpage_image] =>[orig_patent_app_number] => 10112703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178124 [patent_doc_number] => 06760891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Simulator of dynamic circuit for silicon critical path debug' [patent_app_type] => B2 [patent_app_number] => 10/113423 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2880 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760891.pdf [firstpage_image] =>[orig_patent_app_number] => 10113423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6789090 [patent_doc_number] => 20030140329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Method for forming exposure pattern and exposure pattern' [patent_app_type] => new [patent_app_number] => 10/297211 [patent_app_country] => US [patent_app_date] => 2002-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5960 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140329.pdf [firstpage_image] =>[orig_patent_app_number] => 10297211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6831586 [patent_doc_number] => 20030182644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => '(Design rule check)/(electrical rule check) algorithms using a system resolution' [patent_app_type] => new [patent_app_number] => 10/103521 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5050 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182644.pdf [firstpage_image] =>[orig_patent_app_number] => 10103521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6831585 [patent_doc_number] => 20030182643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method for comprehensively verifying design rule checking runsets' [patent_app_type] => new [patent_app_number] => 10/063101 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182643.pdf [firstpage_image] =>[orig_patent_app_number] => 10063101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6675982 [patent_doc_number] => 20030061585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Design system of integrated circuit and its design method and program' [patent_app_type] => new [patent_app_number] => 10/098551 [patent_app_country] => US [patent_app_date] => 2002-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061585.pdf [firstpage_image] =>[orig_patent_app_number] => 10098551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6798584 [patent_doc_number] => 20030177459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed' [patent_app_type] => new [patent_app_number] => 10/098111 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177459.pdf [firstpage_image] =>[orig_patent_app_number] => 10098111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1214646 [patent_doc_number] => 06715134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and apparatus to facilitate generating simulation modules for testing system designs' [patent_app_type] => B2 [patent_app_number] => 10/090651 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2112 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715134.pdf [firstpage_image] =>[orig_patent_app_number] => 10090651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5861458 [patent_doc_number] => 20020124235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Method of forming mask for charged particle beam exposure and processing program of pattern data for forming mask for charged particle beam exposure' [patent_app_type] => new [patent_app_number] => 10/084501 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7814 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124235.pdf [firstpage_image] =>[orig_patent_app_number] => 10084501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1179597 [patent_doc_number] => 06757877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'System and method for identifying and eliminating bottlenecks in integrated circuit designs' [patent_app_type] => B2 [patent_app_number] => 10/083411 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3225 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757877.pdf [firstpage_image] =>[orig_patent_app_number] => 10083411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6265772 [patent_doc_number] => 20020188916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Integrated circuit, integrated circuit design method and hardware description generation method to generate hardware behavior description of integrated circuit' [patent_app_type] => new [patent_app_number] => 10/083341 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188916.pdf [firstpage_image] =>[orig_patent_app_number] => 10083341 [rel_patent_id] =>[rel_patent_doc_number] =>)