Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1046444 [patent_doc_number] => 06868537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method of generating an IC mask using a reduced database' [patent_app_type] => utility [patent_app_number] => 10/082991 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3263 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868537.pdf [firstpage_image] =>[orig_patent_app_number] => 10082991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082991
Method of generating an IC mask using a reduced database Feb 24, 2002 Issued
Array ( [id] => 1210608 [patent_doc_number] => 06718532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Charged particle beam exposure system using aperture mask in semiconductor manufacture' [patent_app_type] => B2 [patent_app_number] => 10/080081 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 7868 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718532.pdf [firstpage_image] =>[orig_patent_app_number] => 10080081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080081
Charged particle beam exposure system using aperture mask in semiconductor manufacture Feb 21, 2002 Issued
Array ( [id] => 6134296 [patent_doc_number] => 20020078426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Cumputer Program Product for Defining Slits in a Bus on a Chip' [patent_app_type] => new [patent_app_number] => 10/077940 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4324 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078426.pdf [firstpage_image] =>[orig_patent_app_number] => 10077940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077940
Computer program product for defining slits in a bus on a chip Feb 19, 2002 Issued
Array ( [id] => 6051730 [patent_doc_number] => 20020170027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Method and apparatus for pre-computing placement costs' [patent_app_type] => new [patent_app_number] => 10/079061 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 20593 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20020170027.pdf [firstpage_image] =>[orig_patent_app_number] => 10079061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079061
Method and apparatus for pre-computing placement costs Feb 19, 2002 Issued
Array ( [id] => 6581006 [patent_doc_number] => 20020166099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method of and system for making a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/078171 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3108 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20020166099.pdf [firstpage_image] =>[orig_patent_app_number] => 10078171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078171
Method of and system for making a semiconductor device Feb 18, 2002 Abandoned
Array ( [id] => 1093062 [patent_doc_number] => 06829757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method and apparatus for generating multi-layer routes' [patent_app_type] => B1 [patent_app_number] => 10/076121 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 97 [patent_no_of_words] => 31065 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829757.pdf [firstpage_image] =>[orig_patent_app_number] => 10076121 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076121
Method and apparatus for generating multi-layer routes Feb 11, 2002 Issued
Array ( [id] => 6649339 [patent_doc_number] => 20020087941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Semiconductor device having embedded array' [patent_app_type] => new [patent_app_number] => 10/067881 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 5392 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087941.pdf [firstpage_image] =>[orig_patent_app_number] => 10067881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067881
Semiconductor device having embedded array Feb 7, 2002 Issued
Array ( [id] => 6211718 [patent_doc_number] => 20020073381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method for designing integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/067820 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5459 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073381.pdf [firstpage_image] =>[orig_patent_app_number] => 10067820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067820
Method for designing integrated circuit device Feb 7, 2002 Issued
Array ( [id] => 7198062 [patent_doc_number] => 20040205610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'System for automated generation of data path macro cells' [patent_app_type] => new [patent_app_number] => 10/068649 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3038 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20040205610.pdf [firstpage_image] =>[orig_patent_app_number] => 10068649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068649
System for automated generation of data path macro cells Feb 4, 2002 Issued
Array ( [id] => 6283497 [patent_doc_number] => 20020108098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method for correcting optical proximity effects' [patent_app_type] => new [patent_app_number] => 10/068441 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20020108098.pdf [firstpage_image] =>[orig_patent_app_number] => 10068441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068441
Method for correcting optical proximity effects Feb 4, 2002 Abandoned
Array ( [id] => 778080 [patent_doc_number] => 07003743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method and system of data processor design by sensitizing logical difference' [patent_app_type] => utility [patent_app_number] => 10/061581 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5393 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003743.pdf [firstpage_image] =>[orig_patent_app_number] => 10061581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061581
Method and system of data processor design by sensitizing logical difference Jan 31, 2002 Issued
Array ( [id] => 1214647 [patent_doc_number] => 06715135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Formal verification method' [patent_app_type] => B2 [patent_app_number] => 10/060261 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3543 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715135.pdf [firstpage_image] =>[orig_patent_app_number] => 10060261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060261
Formal verification method Jan 31, 2002 Issued
Array ( [id] => 6853092 [patent_doc_number] => 20030145295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Critical path analysis' [patent_app_type] => new [patent_app_number] => 10/062591 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3508 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145295.pdf [firstpage_image] =>[orig_patent_app_number] => 10062591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062591
Method and apparatus for improving critical path analysis using gate delay Jan 30, 2002 Issued
Array ( [id] => 381213 [patent_doc_number] => 07310793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Interconnect lines with non-rectilinear terminations' [patent_app_type] => utility [patent_app_number] => 10/061641 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 97 [patent_no_of_words] => 30932 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310793.pdf [firstpage_image] =>[orig_patent_app_number] => 10061641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061641
Interconnect lines with non-rectilinear terminations Jan 30, 2002 Issued
Array ( [id] => 782475 [patent_doc_number] => 06996793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Methods and apparatus for storing and manipulating diagonal interconnect lines of a multidimensional integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/066387 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 11611 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996793.pdf [firstpage_image] =>[orig_patent_app_number] => 10066387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066387
Methods and apparatus for storing and manipulating diagonal interconnect lines of a multidimensional integrated circuit design Jan 30, 2002 Issued
Array ( [id] => 1059097 [patent_doc_number] => 06857110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Design methodology for merging programmable logic into a custom IC' [patent_app_type] => utility [patent_app_number] => 10/067151 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9506 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857110.pdf [firstpage_image] =>[orig_patent_app_number] => 10067151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067151
Design methodology for merging programmable logic into a custom IC Jan 28, 2002 Issued
Array ( [id] => 1155801 [patent_doc_number] => 06779162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method of analyzing and filtering timing runs using common timing characteristics' [patent_app_type] => B2 [patent_app_number] => 10/042101 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2053 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779162.pdf [firstpage_image] =>[orig_patent_app_number] => 10042101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042101
Method of analyzing and filtering timing runs using common timing characteristics Jan 6, 2002 Issued
Array ( [id] => 6369764 [patent_doc_number] => 20020059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => new [patent_app_number] => 10/040852 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11039 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059553.pdf [firstpage_image] =>[orig_patent_app_number] => 10040852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040852
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Dec 27, 2001 Issued
Array ( [id] => 6369764 [patent_doc_number] => 20020059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => new [patent_app_number] => 10/040852 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11039 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059553.pdf [firstpage_image] =>[orig_patent_app_number] => 10040852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040852
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Dec 27, 2001 Issued
Array ( [id] => 6369764 [patent_doc_number] => 20020059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => new [patent_app_number] => 10/040852 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11039 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059553.pdf [firstpage_image] =>[orig_patent_app_number] => 10040852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040852
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Dec 27, 2001 Issued
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