Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6763202 [patent_doc_number] => 20030126564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'CALCULATING INTERCONNECT SWIZZLING PATTERNS FOR CAPACITIVE AND INDUCTIVE NOISE CANCELLATION' [patent_app_type] => new [patent_app_number] => 10/040766 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 13303 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126564.pdf [firstpage_image] =>[orig_patent_app_number] => 10040766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040766
Calculating interconnect swizzling patterns for capacitive and inductive noise cancellation Dec 27, 2001 Issued
Array ( [id] => 6369764 [patent_doc_number] => 20020059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => new [patent_app_number] => 10/040852 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11039 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059553.pdf [firstpage_image] =>[orig_patent_app_number] => 10040852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040852
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Dec 27, 2001 Issued
Array ( [id] => 1027808 [patent_doc_number] => 06886153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Design driven inspection or measurement for semiconductor using recipe' [patent_app_type] => utility [patent_app_number] => 10/029521 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5814 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886153.pdf [firstpage_image] =>[orig_patent_app_number] => 10029521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029521
Design driven inspection or measurement for semiconductor using recipe Dec 20, 2001 Issued
Array ( [id] => 1329549 [patent_doc_number] => 06606739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Scaling method for a digital photolithography system' [patent_app_type] => B2 [patent_app_number] => 10/028479 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 39 [patent_no_of_words] => 7444 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606739.pdf [firstpage_image] =>[orig_patent_app_number] => 10028479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028479
Scaling method for a digital photolithography system Dec 18, 2001 Issued
Array ( [id] => 6670537 [patent_doc_number] => 20030115522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method and program product for designing hierarchical circuit for quiescent current testing' [patent_app_type] => new [patent_app_number] => 10/015751 [patent_app_country] => US [patent_app_date] => 2001-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10332 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115522.pdf [firstpage_image] =>[orig_patent_app_number] => 10015751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015751
Method and program product for designing hierarchical circuit for quiescent current testing Dec 16, 2001 Issued
Array ( [id] => 1292439 [patent_doc_number] => 06643828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method for controlling critical circuits in the design of integrated circuits' [patent_app_type] => B2 [patent_app_number] => 10/016861 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4212 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643828.pdf [firstpage_image] =>[orig_patent_app_number] => 10016861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016861
Method for controlling critical circuits in the design of integrated circuits Dec 13, 2001 Issued
Array ( [id] => 6698258 [patent_doc_number] => 20030110452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Electronic package design with improved power delivery performance' [patent_app_type] => new [patent_app_number] => 10/013641 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4260 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110452.pdf [firstpage_image] =>[orig_patent_app_number] => 10013641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013641
Electronic package design with improved power delivery performance Dec 6, 2001 Issued
Array ( [id] => 7644091 [patent_doc_number] => 06473883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid' [patent_app_type] => B1 [patent_app_number] => 09/997437 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473883.pdf [firstpage_image] =>[orig_patent_app_number] => 09997437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997437
Integrated circuit performance and reliability using angle measurement for a patterned bump layout on a power grid Nov 28, 2001 Issued
Array ( [id] => 6593492 [patent_doc_number] => 20020063252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Simulation circuit for MOS transistor, simulation testing method, netlist of simulation circuit and storage medium storing same' [patent_app_type] => new [patent_app_number] => 09/996251 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8874 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063252.pdf [firstpage_image] =>[orig_patent_app_number] => 09996251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996251
Simulation circuit for MOS transistor, simulation testing method, netlist of simulation circuit and storage medium storing same Nov 27, 2001 Issued
Array ( [id] => 6206007 [patent_doc_number] => 20020070783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Clock control circuit and method' [patent_app_type] => new [patent_app_number] => 09/995517 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12571 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070783.pdf [firstpage_image] =>[orig_patent_app_number] => 09995517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995517
Clock control circuit and method Nov 27, 2001 Issued
Array ( [id] => 6767026 [patent_doc_number] => 20030101426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'System and method for providing isolated fabric interface in high-speed network switching and routing platforms' [patent_app_type] => new [patent_app_number] => 09/995410 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16284 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101426.pdf [firstpage_image] =>[orig_patent_app_number] => 09995410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/995410
System and method for providing isolated fabric interface in high-speed network switching and routing platforms Nov 26, 2001 Abandoned
Array ( [id] => 5791703 [patent_doc_number] => 20020162084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Emulation circuit with a hold time algorithm, logic analyzer and shadow memory' [patent_app_type] => new [patent_app_number] => 09/989774 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13077 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20020162084.pdf [firstpage_image] =>[orig_patent_app_number] => 09989774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989774
Programmable logic device having integrated probing structures Nov 18, 2001 Issued
Array ( [id] => 1011530 [patent_doc_number] => 06901563 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Storing of global parameter defaults and using them over two or more design projects' [patent_app_type] => utility [patent_app_number] => 09/989761 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4032 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/901/06901563.pdf [firstpage_image] =>[orig_patent_app_number] => 09989761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989761
Storing of global parameter defaults and using them over two or more design projects Nov 18, 2001 Issued
Array ( [id] => 1292479 [patent_doc_number] => 06643833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method of localized placement manipulation without extra latency' [patent_app_type] => B1 [patent_app_number] => 09/992651 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3104 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643833.pdf [firstpage_image] =>[orig_patent_app_number] => 09992651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992651
Method of localized placement manipulation without extra latency Nov 15, 2001 Issued
Array ( [id] => 7623747 [patent_doc_number] => 06725430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Process for designing high frequency circuits in multiple domains' [patent_app_type] => B2 [patent_app_number] => 10/011611 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 47 [patent_no_of_words] => 12674 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725430.pdf [firstpage_image] =>[orig_patent_app_number] => 10011611 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011611
Process for designing high frequency circuits in multiple domains Nov 4, 2001 Issued
Array ( [id] => 6659875 [patent_doc_number] => 20030079189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method for generating transition delay fault test patterns' [patent_app_type] => new [patent_app_number] => 09/986211 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3463 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20030079189.pdf [firstpage_image] =>[orig_patent_app_number] => 09986211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986211
Method for generating transition delay fault test patterns Oct 21, 2001 Issued
Array ( [id] => 1280156 [patent_doc_number] => 06654945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Storage medium in which data for designing an integrated circuit is stored and method of fabricating an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/913021 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8428 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654945.pdf [firstpage_image] =>[orig_patent_app_number] => 09913021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/913021
Storage medium in which data for designing an integrated circuit is stored and method of fabricating an integrated circuit Oct 11, 2001 Issued
Array ( [id] => 7631490 [patent_doc_number] => 06665847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Accurate and realistic corner characterization of standard cells' [patent_app_type] => B1 [patent_app_number] => 09/972131 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 14 [patent_no_of_words] => 8485 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665847.pdf [firstpage_image] =>[orig_patent_app_number] => 09972131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972131
Accurate and realistic corner characterization of standard cells Oct 4, 2001 Issued
Array ( [id] => 1602366 [patent_doc_number] => 06493859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of wiring power service terminals to a power network in a semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/682641 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493859.pdf [firstpage_image] =>[orig_patent_app_number] => 09682641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/682641
Method of wiring power service terminals to a power network in a semiconductor integrated circuit Sep 30, 2001 Issued
Array ( [id] => 1431464 [patent_doc_number] => 06523150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method of designing a voltage partitioned wirebond package' [patent_app_type] => B1 [patent_app_number] => 09/682621 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 5818 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523150.pdf [firstpage_image] =>[orig_patent_app_number] => 09682621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/682621
Method of designing a voltage partitioned wirebond package Sep 27, 2001 Issued
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