Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6028831 [patent_doc_number] => 20020017708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Method for manufacturing multi-kind and small quantity semiconductor products in a mass-production line and system thereof' [patent_app_type] => new [patent_app_number] => 09/956151 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017708.pdf [firstpage_image] =>[orig_patent_app_number] => 09956151 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956151
Method for manufacturing multi-kind and small quantity semiconductor products in a mass-production line and system thereof Sep 19, 2001 Issued
Array ( [id] => 6414291 [patent_doc_number] => 20020038448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor integrated circuit device, and method of placement and routing for such device' [patent_app_type] => new [patent_app_number] => 09/951071 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5860 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038448.pdf [firstpage_image] =>[orig_patent_app_number] => 09951071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951071
Semiconductor integrated circuit device, and method of placement and routing for such device Sep 12, 2001 Issued
Array ( [id] => 6085871 [patent_doc_number] => 20020083408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Generating mask layout data for simulation of lithographic processes' [patent_app_type] => new [patent_app_number] => 09/949511 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5611 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083408.pdf [firstpage_image] =>[orig_patent_app_number] => 09949511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949511
Generating mask layout data for simulation of lithographic processes Sep 6, 2001 Issued
Array ( [id] => 6310945 [patent_doc_number] => 20020095649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Optimized emulation and prototyping architecture' [patent_app_type] => new [patent_app_number] => 09/949006 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11121 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20020095649.pdf [firstpage_image] =>[orig_patent_app_number] => 09949006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949006
Optimized emulation and prototyping architecture Sep 5, 2001 Issued
Array ( [id] => 555959 [patent_doc_number] => 07181719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Graphic acquisition method for placement of signal processing applications' [patent_app_type] => utility [patent_app_number] => 10/362731 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181719.pdf [firstpage_image] =>[orig_patent_app_number] => 10362731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362731
Graphic acquisition method for placement of signal processing applications Aug 30, 2001 Issued
Array ( [id] => 6689853 [patent_doc_number] => 20030033579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Method to improve isolation layer fill in a DRAM array area' [patent_app_type] => new [patent_app_number] => 09/928060 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033579.pdf [firstpage_image] =>[orig_patent_app_number] => 09928060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928060
Method to improve isolation layer fill in a DRAM array area Aug 12, 2001 Issued
Array ( [id] => 6899341 [patent_doc_number] => 20010047506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'System and method for controlling current in an integrated circuit' [patent_app_type] => new [patent_app_number] => 09/921168 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5351 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047506.pdf [firstpage_image] =>[orig_patent_app_number] => 09921168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921168
System and method for controlling current in an integrated circuit Aug 1, 2001 Issued
Array ( [id] => 6815090 [patent_doc_number] => 20030074640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Application specific integrated circuit design tool and file structure' [patent_app_type] => new [patent_app_number] => 09/918596 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074640.pdf [firstpage_image] =>[orig_patent_app_number] => 09918596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918596
Application specific integrated circuit design tool and file structure Jul 30, 2001 Issued
Array ( [id] => 5782844 [patent_doc_number] => 20020158299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Mask configurable smart power circuits - applications and GF-NMOS devices' [patent_app_type] => new [patent_app_number] => 09/915571 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10702 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158299.pdf [firstpage_image] =>[orig_patent_app_number] => 09915571 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915571
Mask configurable smart power circuits - applications and GF-NMOS devices Jul 26, 2001 Abandoned
Array ( [id] => 6737097 [patent_doc_number] => 20030014732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'ALTERNATING PHASE SHIFT MASK DESIGN CONFLICT RESOLUTION' [patent_app_type] => new [patent_app_number] => 09/905420 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6111 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014732.pdf [firstpage_image] =>[orig_patent_app_number] => 09905420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905420
Alternating phase shift mask design conflict resolution Jul 12, 2001 Issued
Array ( [id] => 778069 [patent_doc_number] => 07003738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process' [patent_app_type] => utility [patent_app_number] => 09/896071 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6189 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003738.pdf [firstpage_image] =>[orig_patent_app_number] => 09896071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896071
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process Jun 28, 2001 Issued
Array ( [id] => 1309540 [patent_doc_number] => 06629309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Mask-programmable ROM cell' [patent_app_type] => B1 [patent_app_number] => 09/894643 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 9998 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629309.pdf [firstpage_image] =>[orig_patent_app_number] => 09894643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894643
Mask-programmable ROM cell Jun 26, 2001 Issued
Array ( [id] => 6034850 [patent_doc_number] => 20020019730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'System for intellectual property reuse in integrated circuit design' [patent_app_type] => new [patent_app_number] => 09/888332 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8628 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019730.pdf [firstpage_image] =>[orig_patent_app_number] => 09888332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888332
System for intellectual property reuse in integrated circuit design Jun 20, 2001 Issued
Array ( [id] => 6675977 [patent_doc_number] => 20030061580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Simulation method and compiler for hardware/software programming' [patent_app_type] => new [patent_app_number] => 09/886701 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9233 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061580.pdf [firstpage_image] =>[orig_patent_app_number] => 09886701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886701
Simulation method and compiler for hardware/software programming Jun 20, 2001 Issued
Array ( [id] => 1366110 [patent_doc_number] => 06581198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring' [patent_app_type] => B1 [patent_app_number] => 09/681830 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 4551 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581198.pdf [firstpage_image] =>[orig_patent_app_number] => 09681830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681830
Method and arrangement for extracting capacitance in integrated circuits having non Manhattan wiring Jun 12, 2001 Issued
Array ( [id] => 1046441 [patent_doc_number] => 06868535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method and apparatus for optimizing the timing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 09/879841 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2797 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868535.pdf [firstpage_image] =>[orig_patent_app_number] => 09879841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/879841
Method and apparatus for optimizing the timing of integrated circuits Jun 11, 2001 Issued
Array ( [id] => 1260703 [patent_doc_number] => 06668363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Clock supplying circuit and method having enable buffer cells with first and second input terminals' [patent_app_type] => B2 [patent_app_number] => 09/875159 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 13193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668363.pdf [firstpage_image] =>[orig_patent_app_number] => 09875159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875159
Clock supplying circuit and method having enable buffer cells with first and second input terminals Jun 6, 2001 Issued
Array ( [id] => 5999953 [patent_doc_number] => 20020028523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Process for making photomask pattern data and photomask' [patent_app_type] => new [patent_app_number] => 09/854841 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5157 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028523.pdf [firstpage_image] =>[orig_patent_app_number] => 09854841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854841
Process for making photomask pattern data and photomask May 13, 2001 Issued
Array ( [id] => 1348846 [patent_doc_number] => 06598206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and system of modifying integrated circuit power rails' [patent_app_type] => B2 [patent_app_number] => 09/853115 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4804 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598206.pdf [firstpage_image] =>[orig_patent_app_number] => 09853115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853115
Method and system of modifying integrated circuit power rails May 9, 2001 Issued
Array ( [id] => 6752137 [patent_doc_number] => 20030046658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Event-based temporal logic' [patent_app_type] => new [patent_app_number] => 09/847391 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8039 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046658.pdf [firstpage_image] =>[orig_patent_app_number] => 09847391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847391
Event-based temporal logic May 1, 2001 Issued
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