
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6948353
[patent_doc_number] => 20010021990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-13
[patent_title] => 'Method of edsigning semiconductor integrated circuit'
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[patent_app_number] => 09/843687
[patent_app_country] => US
[patent_app_date] => 2001-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0021/20010021990.pdf
[firstpage_image] =>[orig_patent_app_number] => 09843687
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/843687 | Method of designing semiconductor integrated circuit utilizing a scan test function | Apr 29, 2001 | Issued |
Array
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[patent_doc_number] => 06473886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-29
[patent_title] => 'Constant impedance driver circuit including impedance matching with load and a method for designing the same'
[patent_app_type] => B2
[patent_app_number] => 09/821692
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Array
(
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[patent_doc_number] => 20010009031
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[patent_issue_date] => 2001-07-19
[patent_title] => 'Method and apparatus for global routing, and storage medium having global routing program stored therein'
[patent_app_type] => new-utility
[patent_app_number] => 09/800490
[patent_app_country] => US
[patent_app_date] => 2001-03-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800490 | Method and apparatus for global routing, and storage medium having global routing program stored therein | Mar 7, 2001 | Issued |
Array
(
[id] => 1417673
[patent_doc_number] => 06532576
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[patent_issue_date] => 2003-03-11
[patent_title] => 'Cell interconnect delay library for integrated circuit design'
[patent_app_type] => B1
[patent_app_number] => 09/801392
[patent_app_country] => US
[patent_app_date] => 2001-03-07
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Array
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[patent_title] => 'Circuit design apparatus and method'
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Array
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Array
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[patent_title] => 'Method and arrangement for testing the stability of a working point of a circuit'
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Array
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[patent_title] => 'RTL power analysis using gate-level cell power models'
[patent_app_type] => B1
[patent_app_number] => 09/798016
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/794918 | Design and assisting system and method using electromagnetic position | Feb 27, 2001 | Issued |
Array
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[patent_title] => 'Method of design for testability, method of design for integrated circuits and integrated circuits'
[patent_app_type] => B2
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Array
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[patent_title] => 'Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise'
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Array
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Array
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Array
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Array
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Array
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