Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6948353 [patent_doc_number] => 20010021990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Method of edsigning semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/843687 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 26423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021990.pdf [firstpage_image] =>[orig_patent_app_number] => 09843687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843687
Method of designing semiconductor integrated circuit utilizing a scan test function Apr 29, 2001 Issued
Array ( [id] => 7644088 [patent_doc_number] => 06473886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Constant impedance driver circuit including impedance matching with load and a method for designing the same' [patent_app_type] => B2 [patent_app_number] => 09/821692 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3506 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473886.pdf [firstpage_image] =>[orig_patent_app_number] => 09821692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/821692
Constant impedance driver circuit including impedance matching with load and a method for designing the same Mar 29, 2001 Issued
Array ( [id] => 6888037 [patent_doc_number] => 20010009031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-19 [patent_title] => 'Method and apparatus for global routing, and storage medium having global routing program stored therein' [patent_app_type] => new-utility [patent_app_number] => 09/800490 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9601 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009031.pdf [firstpage_image] =>[orig_patent_app_number] => 09800490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800490
Method and apparatus for global routing, and storage medium having global routing program stored therein Mar 7, 2001 Issued
Array ( [id] => 1417673 [patent_doc_number] => 06532576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Cell interconnect delay library for integrated circuit design' [patent_app_type] => B1 [patent_app_number] => 09/801392 [patent_app_country] => US [patent_app_date] => 2001-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1988 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532576.pdf [firstpage_image] =>[orig_patent_app_number] => 09801392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801392
Cell interconnect delay library for integrated circuit design Mar 6, 2001 Issued
Array ( [id] => 6948354 [patent_doc_number] => 20010021991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Circuit design apparatus and method' [patent_app_type] => new [patent_app_number] => 09/796798 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5009 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021991.pdf [firstpage_image] =>[orig_patent_app_number] => 09796798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796798
Circuit design apparatus and method thereof for optimizing a circuit Mar 1, 2001 Issued
Array ( [id] => 5948604 [patent_doc_number] => 20020005572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Integrated circruit and layout method for the same' [patent_app_type] => new [patent_app_number] => 09/798782 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2857 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20020005572.pdf [firstpage_image] =>[orig_patent_app_number] => 09798782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798782
Integrated circuit and layout method for the same using blank area of macrocell Mar 1, 2001 Issued
Array ( [id] => 1197218 [patent_doc_number] => 06732337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method and arrangement for testing the stability of a working point of a circuit' [patent_app_type] => B1 [patent_app_number] => 09/786297 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3038 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732337.pdf [firstpage_image] =>[orig_patent_app_number] => 09786297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/786297
Method and arrangement for testing the stability of a working point of a circuit Feb 28, 2001 Issued
Array ( [id] => 1348894 [patent_doc_number] => 06598209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'RTL power analysis using gate-level cell power models' [patent_app_type] => B1 [patent_app_number] => 09/798016 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9563 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598209.pdf [firstpage_image] =>[orig_patent_app_number] => 09798016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798016
RTL power analysis using gate-level cell power models Feb 27, 2001 Issued
Array ( [id] => 6892599 [patent_doc_number] => 20010018761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Design assisting system and design assisting method' [patent_app_type] => new [patent_app_number] => 09/794918 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9986 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018761.pdf [firstpage_image] =>[orig_patent_app_number] => 09794918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794918
Design and assisting system and method using electromagnetic position Feb 27, 2001 Issued
Array ( [id] => 1221941 [patent_doc_number] => 06708315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Method of design for testability, method of design for integrated circuits and integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/789524 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 68 [patent_no_of_words] => 16412 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708315.pdf [firstpage_image] =>[orig_patent_app_number] => 09789524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789524
Method of design for testability, method of design for integrated circuits and integrated circuits Feb 21, 2001 Issued
Array ( [id] => 1298438 [patent_doc_number] => 06631509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise' [patent_app_type] => B2 [patent_app_number] => 09/771843 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 68 [patent_no_of_words] => 28169 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631509.pdf [firstpage_image] =>[orig_patent_app_number] => 09771843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771843
Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise Jan 28, 2001 Issued
Array ( [id] => 6878163 [patent_doc_number] => 20010002318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'Power bus and method for generating power slits therein' [patent_app_type] => new-utility [patent_app_number] => 09/758367 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4322 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002318.pdf [firstpage_image] =>[orig_patent_app_number] => 09758367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758367
Power bus and method for generating power slits therein Jan 11, 2001 Issued
Array ( [id] => 947845 [patent_doc_number] => 06966045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Method and computer program product for estimating wire loads' [patent_app_type] => utility [patent_app_number] => 09/748901 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 9599 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/966/06966045.pdf [firstpage_image] =>[orig_patent_app_number] => 09748901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748901
Method and computer program product for estimating wire loads Dec 26, 2000 Issued
Array ( [id] => 7105738 [patent_doc_number] => 20010004765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Method of checking exposure patterns formed over photo-mask' [patent_app_type] => new-utility [patent_app_number] => 09/739788 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8242 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004765.pdf [firstpage_image] =>[orig_patent_app_number] => 09739788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739788
Method of checking exposure patterns formed over photo-mask Dec 19, 2000 Issued
Array ( [id] => 7118689 [patent_doc_number] => 20010001881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Methods and media for utilizing symbolic expressions in circuit modules' [patent_app_type] => new-utility [patent_app_number] => 09/741315 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15760 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001881.pdf [firstpage_image] =>[orig_patent_app_number] => 09741315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741315
Methods and media for utilizing symbolic expressions in circuit modules Dec 18, 2000 Abandoned
Array ( [id] => 680472 [patent_doc_number] => 07089523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement' [patent_app_type] => utility [patent_app_number] => 09/737245 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 15242 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089523.pdf [firstpage_image] =>[orig_patent_app_number] => 09737245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737245
Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement Dec 12, 2000 Issued
Array ( [id] => 6211733 [patent_doc_number] => 20020073394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Methodology for increasing yield, manufacturability, and performance of integrated circuits through correction of photolithographic masks' [patent_app_type] => new [patent_app_number] => 09/733412 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3975 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073394.pdf [firstpage_image] =>[orig_patent_app_number] => 09733412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733412
Methodology for increasing yield, manufacturability, and performance of integrated circuits through correction of photolithographic masks Dec 10, 2000 Abandoned
Array ( [id] => 758138 [patent_doc_number] => 07024650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method and apparatus for considering diagonal wiring in placement' [patent_app_type] => utility [patent_app_number] => 09/731891 [patent_app_country] => US [patent_app_date] => 2000-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 15189 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024650.pdf [firstpage_image] =>[orig_patent_app_number] => 09731891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731891
Method and apparatus for considering diagonal wiring in placement Dec 5, 2000 Issued
Array ( [id] => 1424313 [patent_doc_number] => 06539531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes' [patent_app_type] => B2 [patent_app_number] => 09/728050 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 12645 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539531.pdf [firstpage_image] =>[orig_patent_app_number] => 09728050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/728050
Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes Nov 30, 2000 Issued
Array ( [id] => 1382949 [patent_doc_number] => 06574785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Wiring method for semiconductor integrated circuit and computer product using maximum gap between times' [patent_app_type] => B1 [patent_app_number] => 09/722691 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6095 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574785.pdf [firstpage_image] =>[orig_patent_app_number] => 09722691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722691
Wiring method for semiconductor integrated circuit and computer product using maximum gap between times Nov 27, 2000 Issued
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