Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1417787 [patent_doc_number] => 06532585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method and apparatus for application of proximity correction with relative segmentation' [patent_app_type] => B1 [patent_app_number] => 09/714370 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 5986 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532585.pdf [firstpage_image] =>[orig_patent_app_number] => 09714370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714370
Method and apparatus for application of proximity correction with relative segmentation Nov 13, 2000 Issued
Array ( [id] => 1602386 [patent_doc_number] => 06493867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Digital photolithography system for making smooth diagonal components' [patent_app_type] => B1 [patent_app_number] => 09/712730 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 37 [patent_no_of_words] => 6472 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493867.pdf [firstpage_image] =>[orig_patent_app_number] => 09712730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712730
Digital photolithography system for making smooth diagonal components Nov 13, 2000 Issued
Array ( [id] => 1408091 [patent_doc_number] => 06560758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for verifying and representing hardware by decomposition and partitioning' [patent_app_type] => B1 [patent_app_number] => 09/709680 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 12273 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560758.pdf [firstpage_image] =>[orig_patent_app_number] => 09709680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709680
Method for verifying and representing hardware by decomposition and partitioning Nov 8, 2000 Issued
Array ( [id] => 1315016 [patent_doc_number] => 06622291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method and apparatus for physical budgeting during RTL floorplanning' [patent_app_type] => B1 [patent_app_number] => 09/702090 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 17399 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622291.pdf [firstpage_image] =>[orig_patent_app_number] => 09702090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/702090
Method and apparatus for physical budgeting during RTL floorplanning Oct 29, 2000 Issued
Array ( [id] => 1419677 [patent_doc_number] => 06546530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Linear delay element providing linear delay steps' [patent_app_type] => B1 [patent_app_number] => 09/662417 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6936 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546530.pdf [firstpage_image] =>[orig_patent_app_number] => 09662417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662417
Linear delay element providing linear delay steps Sep 13, 2000 Issued
Array ( [id] => 1236676 [patent_doc_number] => 06694489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Test interface for a configurable system on-chip' [patent_app_type] => B1 [patent_app_number] => 09/649101 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5370 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694489.pdf [firstpage_image] =>[orig_patent_app_number] => 09649101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649101
Test interface for a configurable system on-chip Aug 22, 2000 Issued
Array ( [id] => 1382874 [patent_doc_number] => 06574781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Design methodology for inserting RAM clock delays' [patent_app_type] => B1 [patent_app_number] => 09/642101 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4052 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574781.pdf [firstpage_image] =>[orig_patent_app_number] => 09642101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642101
Design methodology for inserting RAM clock delays Aug 20, 2000 Issued
Array ( [id] => 1413063 [patent_doc_number] => 06553556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Programmable element latch circuit' [patent_app_type] => B1 [patent_app_number] => 09/640741 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3475 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553556.pdf [firstpage_image] =>[orig_patent_app_number] => 09640741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640741
Programmable element latch circuit Aug 17, 2000 Issued
Array ( [id] => 1592599 [patent_doc_number] => 06360356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => B1 [patent_app_number] => 09/634927 [patent_app_country] => US [patent_app_date] => 2000-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10738 [patent_no_of_claims] => 92 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360356.pdf [firstpage_image] =>[orig_patent_app_number] => 09634927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/634927
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Aug 7, 2000 Issued
Array ( [id] => 1396932 [patent_doc_number] => 06567969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Configurable logic array including lookup table means for generating functions of different numbers of input terms' [patent_app_type] => B1 [patent_app_number] => 09/632319 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 26013 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567969.pdf [firstpage_image] =>[orig_patent_app_number] => 09632319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632319
Configurable logic array including lookup table means for generating functions of different numbers of input terms Aug 3, 2000 Issued
Array ( [id] => 7642309 [patent_doc_number] => 06430737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Convergence technique for model-based optical and process correction' [patent_app_type] => B1 [patent_app_number] => 09/613214 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4945 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430737.pdf [firstpage_image] =>[orig_patent_app_number] => 09613214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613214
Convergence technique for model-based optical and process correction Jul 9, 2000 Issued
Array ( [id] => 685051 [patent_doc_number] => 07086027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method and apparatus for constraint graph based layout compaction for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/332111 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6027 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/086/07086027.pdf [firstpage_image] =>[orig_patent_app_number] => 10332111 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/332111
Method and apparatus for constraint graph based layout compaction for integrated circuits Jul 2, 2000 Issued
Array ( [id] => 1533405 [patent_doc_number] => 06481000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits' [patent_app_type] => B1 [patent_app_number] => 09/608061 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 42 [patent_no_of_words] => 15146 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/481/06481000.pdf [firstpage_image] =>[orig_patent_app_number] => 09608061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608061
Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits Jun 28, 2000 Issued
Array ( [id] => 1386967 [patent_doc_number] => 06571378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method and apparatus for a N-NARY logic circuit using capacitance isolation' [patent_app_type] => B1 [patent_app_number] => 09/587729 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6760 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571378.pdf [firstpage_image] =>[orig_patent_app_number] => 09587729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587729
Method and apparatus for a N-NARY logic circuit using capacitance isolation Jun 4, 2000 Issued
Array ( [id] => 1553263 [patent_doc_number] => 06446249 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory' [patent_app_type] => B1 [patent_app_number] => 09/570142 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 36 [patent_no_of_words] => 13077 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446249.pdf [firstpage_image] =>[orig_patent_app_number] => 09570142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570142
Emulation circuit with a hold time algorithm, logic and analyzer and shadow memory May 11, 2000 Issued
Array ( [id] => 7634933 [patent_doc_number] => 06381733 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'System and method for instantiating logic blocks within an FPGA' [patent_app_type] => B1 [patent_app_number] => 09/568017 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2482 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381733.pdf [firstpage_image] =>[orig_patent_app_number] => 09568017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/568017
System and method for instantiating logic blocks within an FPGA May 9, 2000 Issued
Array ( [id] => 4337968 [patent_doc_number] => 06249901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Memory characterization system' [patent_app_type] => 1 [patent_app_number] => 9/564235 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 15671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249901.pdf [firstpage_image] =>[orig_patent_app_number] => 564235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564235
Memory characterization system May 3, 2000 Issued
Array ( [id] => 1410541 [patent_doc_number] => 06557147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and apparatus for evaluating a circuit' [patent_app_type] => B1 [patent_app_number] => 09/562309 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6146 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557147.pdf [firstpage_image] =>[orig_patent_app_number] => 09562309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562309
Method and apparatus for evaluating a circuit Apr 30, 2000 Issued
Array ( [id] => 1533362 [patent_doc_number] => 06480990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Application specific integrated circuit with spaced spare logic gate subgroups and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/561725 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5983 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480990.pdf [firstpage_image] =>[orig_patent_app_number] => 09561725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561725
Application specific integrated circuit with spaced spare logic gate subgroups and method of fabrication Apr 30, 2000 Issued
Array ( [id] => 1472153 [patent_doc_number] => 06460170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Connection block for interfacing a plurality of printed circuit boards' [patent_app_type] => B1 [patent_app_number] => 09/561808 [patent_app_country] => US [patent_app_date] => 2000-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4092 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460170.pdf [firstpage_image] =>[orig_patent_app_number] => 09561808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/561808
Connection block for interfacing a plurality of printed circuit boards Apr 28, 2000 Issued
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