Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1604541 [patent_doc_number] => 06434727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Methods of making hard macro cell using timing interval' [patent_app_type] => B1 [patent_app_number] => 09/414435 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3359 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434727.pdf [firstpage_image] =>[orig_patent_app_number] => 09414435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414435
Methods of making hard macro cell using timing interval Oct 6, 1999 Issued
Array ( [id] => 1519818 [patent_doc_number] => 06421819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Integrated circuit layout designing system and power source eliminating method to be employed in the same using arranging power blocks' [patent_app_type] => B1 [patent_app_number] => 09/413493 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4570 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421819.pdf [firstpage_image] =>[orig_patent_app_number] => 09413493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413493
Integrated circuit layout designing system and power source eliminating method to be employed in the same using arranging power blocks Oct 5, 1999 Issued
Array ( [id] => 1501841 [patent_doc_number] => 06405359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for backside failure analysis requiring simple bias conditions' [patent_app_type] => B1 [patent_app_number] => 09/412206 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405359.pdf [firstpage_image] =>[orig_patent_app_number] => 09412206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412206
Method for backside failure analysis requiring simple bias conditions Oct 4, 1999 Issued
Array ( [id] => 1513504 [patent_doc_number] => 06442734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for detecting the type of interface to which a peripheral device is connected' [patent_app_type] => B1 [patent_app_number] => 09/410413 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5682 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442734.pdf [firstpage_image] =>[orig_patent_app_number] => 09410413 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410413
Method and apparatus for detecting the type of interface to which a peripheral device is connected Sep 30, 1999 Issued
Array ( [id] => 1472165 [patent_doc_number] => 06460174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Methods and models for use in designing an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/410641 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8823 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460174.pdf [firstpage_image] =>[orig_patent_app_number] => 09410641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410641
Methods and models for use in designing an integrated circuit Sep 30, 1999 Issued
Array ( [id] => 1602357 [patent_doc_number] => 06493854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus for placing repeaters in a network of an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/411725 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 8136 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493854.pdf [firstpage_image] =>[orig_patent_app_number] => 09411725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411725
Method and apparatus for placing repeaters in a network of an integrated circuit Sep 30, 1999 Issued
Array ( [id] => 4382205 [patent_doc_number] => 06256769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Printed circuit board routing techniques' [patent_app_type] => 1 [patent_app_number] => 9/410269 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5211 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256769.pdf [firstpage_image] =>[orig_patent_app_number] => 410269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410269
Printed circuit board routing techniques Sep 29, 1999 Issued
Array ( [id] => 1557754 [patent_doc_number] => 06401233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Semiconductor integrated circuit wiring condition processing method' [patent_app_type] => B1 [patent_app_number] => 09/405082 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6927 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401233.pdf [firstpage_image] =>[orig_patent_app_number] => 09405082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405082
Semiconductor integrated circuit wiring condition processing method Sep 26, 1999 Issued
Array ( [id] => 1475212 [patent_doc_number] => 06408425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method of designing circuit with field effect transistor and method of determining parameters of model used in such designing method' [patent_app_type] => B1 [patent_app_number] => 09/405690 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4385 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408425.pdf [firstpage_image] =>[orig_patent_app_number] => 09405690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405690
Method of designing circuit with field effect transistor and method of determining parameters of model used in such designing method Sep 23, 1999 Issued
Array ( [id] => 1585126 [patent_doc_number] => 06449752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Digital circuit verification with automated specification enumeration' [patent_app_type] => B1 [patent_app_number] => 09/404278 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4251 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449752.pdf [firstpage_image] =>[orig_patent_app_number] => 09404278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404278
Digital circuit verification with automated specification enumeration Sep 22, 1999 Issued
Array ( [id] => 7629931 [patent_doc_number] => 06637008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Electronic holding circuit and adjusting method thereof using a probabilistic searching technique' [patent_app_type] => B1 [patent_app_number] => 09/397636 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 48 [patent_no_of_words] => 22151 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/637/06637008.pdf [firstpage_image] =>[orig_patent_app_number] => 09397636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397636
Electronic holding circuit and adjusting method thereof using a probabilistic searching technique Sep 15, 1999 Issued
Array ( [id] => 1525055 [patent_doc_number] => 06415418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'System and method for disseminating functional blocks to an on-line redundant controller' [patent_app_type] => B1 [patent_app_number] => 09/384507 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3766 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415418.pdf [firstpage_image] =>[orig_patent_app_number] => 09384507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384507
System and method for disseminating functional blocks to an on-line redundant controller Aug 26, 1999 Issued
Array ( [id] => 4271359 [patent_doc_number] => 06223330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'System and method for designing integrated circuits using cells with multiple unrelated outputs' [patent_app_type] => 1 [patent_app_number] => 9/382361 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4601 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223330.pdf [firstpage_image] =>[orig_patent_app_number] => 382361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382361
System and method for designing integrated circuits using cells with multiple unrelated outputs Aug 23, 1999 Issued
Array ( [id] => 4281752 [patent_doc_number] => 06260176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and system for simulating and making a phase lock loop circuit' [patent_app_type] => 1 [patent_app_number] => 9/372411 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6786 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260176.pdf [firstpage_image] =>[orig_patent_app_number] => 372411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372411
Method and system for simulating and making a phase lock loop circuit Aug 9, 1999 Issued
Array ( [id] => 1419566 [patent_doc_number] => 06546522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Signal-to-noise ratio optimization of multiple-response design-of-experiment' [patent_app_type] => B1 [patent_app_number] => 09/369905 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2325 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546522.pdf [firstpage_image] =>[orig_patent_app_number] => 09369905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369905
Signal-to-noise ratio optimization of multiple-response design-of-experiment Aug 5, 1999 Issued
Array ( [id] => 1553238 [patent_doc_number] => 06446244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and circuit configuration for producing sinusoidal/cosinusoidal oscillations' [patent_app_type] => B1 [patent_app_number] => 09/341887 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1701 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446244.pdf [firstpage_image] =>[orig_patent_app_number] => 09341887 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/341887
Method and circuit configuration for producing sinusoidal/cosinusoidal oscillations Jul 14, 1999 Issued
Array ( [id] => 1604550 [patent_doc_number] => 06434736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Location based timing scheme in memory design' [patent_app_type] => B1 [patent_app_number] => 09/351100 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4390 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434736.pdf [firstpage_image] =>[orig_patent_app_number] => 09351100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351100
Location based timing scheme in memory design Jul 7, 1999 Issued
Array ( [id] => 1501804 [patent_doc_number] => 06405352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method and system for analyzing wire-only changes to a microprocessor design using delta model' [patent_app_type] => B1 [patent_app_number] => 09/343448 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3082 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405352.pdf [firstpage_image] =>[orig_patent_app_number] => 09343448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343448
Method and system for analyzing wire-only changes to a microprocessor design using delta model Jun 29, 1999 Issued
Array ( [id] => 1604540 [patent_doc_number] => 06434726 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'System and method of transmission using coplanar bond wires' [patent_app_type] => B1 [patent_app_number] => 09/342809 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3287 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434726.pdf [firstpage_image] =>[orig_patent_app_number] => 09342809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342809
System and method of transmission using coplanar bond wires Jun 28, 1999 Issued
Array ( [id] => 1580568 [patent_doc_number] => 06470478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method and system for counting events within a simulation model' [patent_app_type] => B1 [patent_app_number] => 09/345163 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470478.pdf [firstpage_image] =>[orig_patent_app_number] => 09345163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345163
Method and system for counting events within a simulation model Jun 28, 1999 Issued
Menu