Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4392847 [patent_doc_number] => 06289497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and apparatus for N-NARY hardware description language' [patent_app_type] => 1 [patent_app_number] => 9/210408 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 10262 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289497.pdf [firstpage_image] =>[orig_patent_app_number] => 210408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210408
Method and apparatus for N-NARY hardware description language Dec 10, 1998 Issued
Array ( [id] => 1490406 [patent_doc_number] => 06367065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation' [patent_app_type] => B1 [patent_app_number] => 09/210410 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 11228 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367065.pdf [firstpage_image] =>[orig_patent_app_number] => 09210410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210410
Method and apparatus for N-Nary logic circuit design tool with precharge circuit evaluation Dec 10, 1998 Issued
Array ( [id] => 4400000 [patent_doc_number] => 06295635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters' [patent_app_type] => 1 [patent_app_number] => 9/193296 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295635.pdf [firstpage_image] =>[orig_patent_app_number] => 193296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193296
Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters Nov 16, 1998 Issued
Array ( [id] => 4404863 [patent_doc_number] => 06263475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for optimizing component placement in designing a semiconductor device by using a cost value' [patent_app_type] => 1 [patent_app_number] => 9/192231 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4167 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263475.pdf [firstpage_image] =>[orig_patent_app_number] => 192231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192231
Method for optimizing component placement in designing a semiconductor device by using a cost value Nov 15, 1998 Issued
Array ( [id] => 1319576 [patent_doc_number] => 06618847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Power stabilizer using under-utilized standard cells' [patent_app_type] => B1 [patent_app_number] => 09/191494 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618847.pdf [firstpage_image] =>[orig_patent_app_number] => 09191494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191494
Power stabilizer using under-utilized standard cells Nov 12, 1998 Issued
Array ( [id] => 4377571 [patent_doc_number] => 06219823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for deciding a wiring route and for detecting a critical cut' [patent_app_type] => 1 [patent_app_number] => 9/190735 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 11931 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219823.pdf [firstpage_image] =>[orig_patent_app_number] => 190735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190735
Method and apparatus for deciding a wiring route and for detecting a critical cut Nov 11, 1998 Issued
Array ( [id] => 4412909 [patent_doc_number] => 06298467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and system for reducing hysteresis effect in SOI CMOS circuits' [patent_app_type] => 1 [patent_app_number] => 9/189423 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5414 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298467.pdf [firstpage_image] =>[orig_patent_app_number] => 189423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189423
Method and system for reducing hysteresis effect in SOI CMOS circuits Nov 9, 1998 Issued
Array ( [id] => 4337955 [patent_doc_number] => 06249900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method of designing an LSI pattern to be formed on a specimen with a bent portion' [patent_app_type] => 1 [patent_app_number] => 9/176109 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249900.pdf [firstpage_image] =>[orig_patent_app_number] => 176109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176109
Method of designing an LSI pattern to be formed on a specimen with a bent portion Oct 20, 1998 Issued
Array ( [id] => 4325311 [patent_doc_number] => 06327694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Cell placement apparatus and method, and computer readable record medium having cell placement program recorded thereon' [patent_app_type] => 1 [patent_app_number] => 9/176260 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 10518 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327694.pdf [firstpage_image] =>[orig_patent_app_number] => 176260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176260
Cell placement apparatus and method, and computer readable record medium having cell placement program recorded thereon Oct 19, 1998 Issued
Array ( [id] => 4326574 [patent_doc_number] => 06253362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of designing dummy wiring' [patent_app_type] => 1 [patent_app_number] => 9/175582 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3252 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253362.pdf [firstpage_image] =>[orig_patent_app_number] => 175582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175582
Method of designing dummy wiring Oct 19, 1998 Issued
Array ( [id] => 1592589 [patent_doc_number] => 06360354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Automatic arrangement of wiring patterns in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/175273 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6107 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360354.pdf [firstpage_image] =>[orig_patent_app_number] => 09175273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175273
Automatic arrangement of wiring patterns in semiconductor device Oct 19, 1998 Issued
Array ( [id] => 4274360 [patent_doc_number] => 06209120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Verifying hardware in its software context and vice-versa' [patent_app_type] => 1 [patent_app_number] => 9/172484 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7221 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209120.pdf [firstpage_image] =>[orig_patent_app_number] => 172484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172484
Verifying hardware in its software context and vice-versa Oct 13, 1998 Issued
Array ( [id] => 4293214 [patent_doc_number] => 06247163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and system of latch mapping for combinational equivalence checking' [patent_app_type] => 1 [patent_app_number] => 9/172708 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247163.pdf [firstpage_image] =>[orig_patent_app_number] => 172708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172708
Method and system of latch mapping for combinational equivalence checking Oct 12, 1998 Issued
Array ( [id] => 4423171 [patent_doc_number] => 06272667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and apparatus for clock gated logic circuits to reduce electric power consumption' [patent_app_type] => 1 [patent_app_number] => 9/168961 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 13021 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272667.pdf [firstpage_image] =>[orig_patent_app_number] => 168961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/168961
Method and apparatus for clock gated logic circuits to reduce electric power consumption Oct 8, 1998 Issued
Array ( [id] => 4427352 [patent_doc_number] => 06226775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor integrated circuit designing method of an interconnection thereof and recording medium in which the method is recorded for empty area' [patent_app_type] => 1 [patent_app_number] => 9/139738 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3291 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226775.pdf [firstpage_image] =>[orig_patent_app_number] => 139738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139738
Semiconductor integrated circuit designing method of an interconnection thereof and recording medium in which the method is recorded for empty area Aug 24, 1998 Issued
Array ( [id] => 1568756 [patent_doc_number] => 06339836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Automated design partitioning' [patent_app_type] => B1 [patent_app_number] => 09/139156 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7703 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339836.pdf [firstpage_image] =>[orig_patent_app_number] => 09139156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139156
Automated design partitioning Aug 23, 1998 Issued
Array ( [id] => 1452525 [patent_doc_number] => 06370675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Semiconductor integrated circuit design and evaluation system using cycle base timing' [patent_app_type] => B1 [patent_app_number] => 09/135892 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370675.pdf [firstpage_image] =>[orig_patent_app_number] => 09135892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135892
Semiconductor integrated circuit design and evaluation system using cycle base timing Aug 17, 1998 Issued
Array ( [id] => 4271315 [patent_doc_number] => 06223327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Cell hierarchy verification method and apparatus for LSI layout' [patent_app_type] => 1 [patent_app_number] => 9/134937 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 38 [patent_no_of_words] => 6909 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223327.pdf [firstpage_image] =>[orig_patent_app_number] => 134937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134937
Cell hierarchy verification method and apparatus for LSI layout Aug 16, 1998 Issued
Array ( [id] => 4404897 [patent_doc_number] => 06263478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'System and method for generating and using stage-based constraints for timing-driven design' [patent_app_type] => 1 [patent_app_number] => 9/132381 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6525 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263478.pdf [firstpage_image] =>[orig_patent_app_number] => 132381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132381
System and method for generating and using stage-based constraints for timing-driven design Aug 10, 1998 Issued
Array ( [id] => 4377557 [patent_doc_number] => 06219822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and system for tuning of components for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/129717 [patent_app_country] => US [patent_app_date] => 1998-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7077 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219822.pdf [firstpage_image] =>[orig_patent_app_number] => 129717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129717
Method and system for tuning of components for integrated circuits Aug 4, 1998 Issued
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