Jeffrey T. Knapp

Array ( [id] => 4350624 [patent_doc_number] => 06321368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'LSI layout designing apparatus, computer-implemented method of designing LSI layout and computer readable storage medium' [patent_app_type] => 1 [patent_app_number] => 9/129426 [patent_app_country] => US [patent_app_date] => 1998-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6488 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321368.pdf [firstpage_image] =>[orig_patent_app_number] => 129426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1490341 [patent_doc_number] => 06367051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'System and method for concurrent buffer insertion and placement of logic gates' [patent_app_type] => B1 [patent_app_number] => 09/096810 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2663 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367051.pdf [firstpage_image] =>[orig_patent_app_number] => 09096810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4281766 [patent_doc_number] => 06260177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Automatic configuration of gate array cells using a standard cell function library' [patent_app_type] => 1 [patent_app_number] => 9/079946 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260177.pdf [firstpage_image] =>[orig_patent_app_number] => 079946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324714 [patent_doc_number] => 06189130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'System and method for determining density maps in hierarchical designs' [patent_app_type] => 1 [patent_app_number] => 9/070482 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4999 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189130.pdf [firstpage_image] =>[orig_patent_app_number] => 070482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425036 [patent_doc_number] => 06230300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for the optimization of a tree depth for clock distribution in semiconductor integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/065425 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4316 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230300.pdf [firstpage_image] =>[orig_patent_app_number] => 065425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374824 [patent_doc_number] => 06175947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization' [patent_app_type] => 1 [patent_app_number] => 9/062853 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7539 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175947.pdf [firstpage_image] =>[orig_patent_app_number] => 062853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305366 [patent_doc_number] => 06269469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method and apparatus for parallel routing locking mechanism' [patent_app_type] => 1 [patent_app_number] => 9/062418 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 54 [patent_no_of_words] => 20559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269469.pdf [firstpage_image] =>[orig_patent_app_number] => 062418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4392816 [patent_doc_number] => 06289495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method and apparatus for local optimization of the global routing' [patent_app_type] => 1 [patent_app_number] => 9/062205 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 54 [patent_no_of_words] => 20484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289495.pdf [firstpage_image] =>[orig_patent_app_number] => 062205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425058 [patent_doc_number] => 06230306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for minimization of process defects while routing' [patent_app_type] => 1 [patent_app_number] => 9/062310 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 54 [patent_no_of_words] => 20576 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230306.pdf [firstpage_image] =>[orig_patent_app_number] => 062310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6892597 [patent_doc_number] => 20010018759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'METHOD AND APPARATUS FOR PARALLEL SIMULTANEOUS GLOBAL AND DETAIL ROUTING' [patent_app_type] => new [patent_app_number] => 09/062309 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 20728 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018759.pdf [firstpage_image] =>[orig_patent_app_number] => 09062309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261305 [patent_doc_number] => 06167560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'One-cold encoding method for low power operation in a complex programmable logic device' [patent_app_type] => 1 [patent_app_number] => 9/061805 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5097 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167560.pdf [firstpage_image] =>[orig_patent_app_number] => 061805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4271302 [patent_doc_number] => 06223326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for analyzing performance and density of a source design module for a target programmable gate array' [patent_app_type] => 1 [patent_app_number] => 9/058003 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4408 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223326.pdf [firstpage_image] =>[orig_patent_app_number] => 058003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4274346 [patent_doc_number] => 06209119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Apparatus and method for synthesizing module' [patent_app_type] => 1 [patent_app_number] => 9/057477 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8024 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209119.pdf [firstpage_image] =>[orig_patent_app_number] => 057477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425048 [patent_doc_number] => 06230304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of designing a constraint-driven integrated circuit layout' [patent_app_type] => 1 [patent_app_number] => 9/054319 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 35 [patent_no_of_words] => 12046 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230304.pdf [firstpage_image] =>[orig_patent_app_number] => 054319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123700 [patent_doc_number] => 06058257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Integrated circuit, design method for the same, and memory storing the program for executing the design method' [patent_app_type] => 1 [patent_app_number] => 9/053045 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 10863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058257.pdf [firstpage_image] =>[orig_patent_app_number] => 053045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380494 [patent_doc_number] => 06192506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Controller for solving logic' [patent_app_type] => 1 [patent_app_number] => 9/052510 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6729 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192506.pdf [firstpage_image] =>[orig_patent_app_number] => 052510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1572646 [patent_doc_number] => 06378110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Layer-based rule checking for an integrated circuit layout' [patent_app_type] => B1 [patent_app_number] => 09/053007 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3972 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378110.pdf [firstpage_image] =>[orig_patent_app_number] => 09053007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425033 [patent_doc_number] => 06230299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 9/052895 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4752 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230299.pdf [firstpage_image] =>[orig_patent_app_number] => 052895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4337997 [patent_doc_number] => 06249903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design' [patent_app_type] => 1 [patent_app_number] => 9/052915 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 6231 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249903.pdf [firstpage_image] =>[orig_patent_app_number] => 052915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4311112 [patent_doc_number] => 06212665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Efficient power analysis method for logic cells with many output switchings' [patent_app_type] => 1 [patent_app_number] => 9/049681 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9986 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212665.pdf [firstpage_image] =>[orig_patent_app_number] => 049681 [rel_patent_id] =>[rel_patent_doc_number] =>)