Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4426784 [patent_doc_number] => 06178540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Profile design for wire bonding' [patent_app_type] => 1 [patent_app_number] => 9/038003 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 3644 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178540.pdf [firstpage_image] =>[orig_patent_app_number] => 038003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038003
Profile design for wire bonding Mar 10, 1998 Issued
Array ( [id] => 4148506 [patent_doc_number] => 06128770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)' [patent_app_type] => 1 [patent_app_number] => 9/037095 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 87 [patent_no_of_words] => 24746 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128770.pdf [firstpage_image] =>[orig_patent_app_number] => 037095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/037095
Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block) Mar 8, 1998 Issued
Array ( [id] => 1466525 [patent_doc_number] => 06393601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method' [patent_app_type] => B1 [patent_app_number] => 09/034382 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 12806 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393601.pdf [firstpage_image] =>[orig_patent_app_number] => 09034382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034382
Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method Mar 3, 1998 Issued
Array ( [id] => 4326465 [patent_doc_number] => 06253355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for fast estimation of step response bound due to capacitance coupling for RC circuits' [patent_app_type] => 1 [patent_app_number] => 9/031012 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253355.pdf [firstpage_image] =>[orig_patent_app_number] => 031012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031012
Method for fast estimation of step response bound due to capacitance coupling for RC circuits Feb 25, 1998 Issued
Array ( [id] => 1585153 [patent_doc_number] => 06449757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Hierarchical semiconductor design' [patent_app_type] => B1 [patent_app_number] => 09/031398 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9013 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449757.pdf [firstpage_image] =>[orig_patent_app_number] => 09031398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031398
Hierarchical semiconductor design Feb 25, 1998 Issued
Array ( [id] => 4404954 [patent_doc_number] => 06263483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of accessing the generic netlist created by synopsys design compilier' [patent_app_type] => 1 [patent_app_number] => 9/027512 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 57 [patent_no_of_words] => 44543 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263483.pdf [firstpage_image] =>[orig_patent_app_number] => 027512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027512
Method of accessing the generic netlist created by synopsys design compilier Feb 19, 1998 Issued
Array ( [id] => 4392760 [patent_doc_number] => 06289491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Netlist analysis tool by degree of conformity' [patent_app_type] => 1 [patent_app_number] => 9/027501 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 57 [patent_no_of_words] => 44619 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289491.pdf [firstpage_image] =>[orig_patent_app_number] => 027501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027501
Netlist analysis tool by degree of conformity Feb 19, 1998 Issued
Array ( [id] => 4404885 [patent_doc_number] => 06263477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Layout information generating apparatus and method thereof' [patent_app_type] => 1 [patent_app_number] => 9/023765 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 6992 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263477.pdf [firstpage_image] =>[orig_patent_app_number] => 023765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023765
Layout information generating apparatus and method thereof Feb 12, 1998 Issued
Array ( [id] => 4377529 [patent_doc_number] => 06219820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Printed circuit board design device' [patent_app_type] => 1 [patent_app_number] => 9/020405 [patent_app_country] => US [patent_app_date] => 1998-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6156 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219820.pdf [firstpage_image] =>[orig_patent_app_number] => 020405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020405
Printed circuit board design device Feb 8, 1998 Issued
Array ( [id] => 4258508 [patent_doc_number] => 06145117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement based information' [patent_app_type] => 1 [patent_app_number] => 9/015602 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10710 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145117.pdf [firstpage_image] =>[orig_patent_app_number] => 015602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015602
Creating optimized physical implementations from high-level descriptions of electronic design using placement based information Jan 29, 1998 Issued
Array ( [id] => 4291298 [patent_doc_number] => 06308310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'System for avoiding electromigration in LSI circuits' [patent_app_type] => 1 [patent_app_number] => 9/004329 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5628 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308310.pdf [firstpage_image] =>[orig_patent_app_number] => 004329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004329
System for avoiding electromigration in LSI circuits Jan 7, 1998 Issued
Array ( [id] => 4198199 [patent_doc_number] => 06077309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method and apparatus for locating coordinated starting points for routing a differential pair of traces' [patent_app_type] => 1 [patent_app_number] => 9/004107 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4565 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077309.pdf [firstpage_image] =>[orig_patent_app_number] => 004107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004107
Method and apparatus for locating coordinated starting points for routing a differential pair of traces Jan 6, 1998 Issued
Array ( [id] => 4134466 [patent_doc_number] => 06072943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Integrated bus controller and terminating chip' [patent_app_type] => 1 [patent_app_number] => 9/001094 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13764 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072943.pdf [firstpage_image] =>[orig_patent_app_number] => 001094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001094
Integrated bus controller and terminating chip Dec 29, 1997 Issued
Array ( [id] => 4054063 [patent_doc_number] => 05909377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Method for manufacturing a power bus on a chip' [patent_app_type] => 1 [patent_app_number] => 8/997605 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909377.pdf [firstpage_image] =>[orig_patent_app_number] => 997605 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997605
Method for manufacturing a power bus on a chip Dec 22, 1997 Issued
Array ( [id] => 4305423 [patent_doc_number] => 06269472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Optical proximity correction method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/991785 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9561 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269472.pdf [firstpage_image] =>[orig_patent_app_number] => 991785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991785
Optical proximity correction method and apparatus Dec 11, 1997 Issued
Array ( [id] => 4156447 [patent_doc_number] => 06061507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Scheduling diagnostic testing of automated equipment for testing integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/988580 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3766 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061507.pdf [firstpage_image] =>[orig_patent_app_number] => 988580 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988580
Scheduling diagnostic testing of automated equipment for testing integrated circuit devices Dec 10, 1997 Issued
Array ( [id] => 4146662 [patent_doc_number] => 06113646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of selecting layout of integrated circuit probe card' [patent_app_type] => 1 [patent_app_number] => 8/984726 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/113/06113646.pdf [firstpage_image] =>[orig_patent_app_number] => 984726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984726
Method of selecting layout of integrated circuit probe card Dec 3, 1997 Issued
Array ( [id] => 4123671 [patent_doc_number] => 06058255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'JTAG instruction decode test register and method' [patent_app_type] => 1 [patent_app_number] => 8/980497 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4888 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058255.pdf [firstpage_image] =>[orig_patent_app_number] => 980497 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980497
JTAG instruction decode test register and method Nov 30, 1997 Issued
Array ( [id] => 1540737 [patent_doc_number] => 06490714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Apparatus and method for in-system programming of a field programmable logic device using device-specific characterization data' [patent_app_type] => B1 [patent_app_number] => 08/975835 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2639 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490714.pdf [firstpage_image] =>[orig_patent_app_number] => 08975835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975835
Apparatus and method for in-system programming of a field programmable logic device using device-specific characterization data Nov 20, 1997 Issued
Array ( [id] => 4392801 [patent_doc_number] => 06289494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Optimized emulation and prototyping architecture' [patent_app_type] => 1 [patent_app_number] => 8/968401 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 10943 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289494.pdf [firstpage_image] =>[orig_patent_app_number] => 968401 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968401
Optimized emulation and prototyping architecture Nov 11, 1997 Issued
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