
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4424813
[patent_doc_number] => 06266799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Multi-phase data/clock recovery circuitry and methods for implementing same'
[patent_app_type] => 1
[patent_app_number] => 8/967087
[patent_app_country] => US
[patent_app_date] => 1997-11-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/266/06266799.pdf
[firstpage_image] =>[orig_patent_app_number] => 967087
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/967087 | Multi-phase data/clock recovery circuitry and methods for implementing same | Nov 9, 1997 | Issued |
Array
(
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[patent_doc_number] => 06212669
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Method for verifying and representing hardware by decomposition and partitioning'
[patent_app_type] => 1
[patent_app_number] => 8/964904
[patent_app_country] => US
[patent_app_date] => 1997-11-05
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 964904
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/964904 | Method for verifying and representing hardware by decomposition and partitioning | Nov 4, 1997 | Issued |
| 08/960408 | INTEGRATED CIRCUIT ASSEMBLY HAVING OUTPUT PADS WITH PROGRAMMABLE CHARACTERISTICS AND METHOD OF OPERATION | Oct 28, 1997 | Abandoned |
Array
(
[id] => 4099932
[patent_doc_number] => 06026226
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[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Local compilation in context within a design hierarchy'
[patent_app_type] => 1
[patent_app_number] => 8/958798
[patent_app_country] => US
[patent_app_date] => 1997-10-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/958798 | Local compilation in context within a design hierarchy | Oct 26, 1997 | Issued |
Array
(
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[patent_doc_number] => 06317860
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Electronic design automation tool for display of design profile'
[patent_app_type] => 1
[patent_app_number] => 8/958431
[patent_app_country] => US
[patent_app_date] => 1997-10-27
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Array
(
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[patent_doc_number] => 05991533
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Verification support system'
[patent_app_type] => 1
[patent_app_number] => 8/948992
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[patent_app_date] => 1997-10-10
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Array
(
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[patent_doc_number] => 06120551
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[patent_title] => 'Hardwire logic device emulating an FPGA'
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[patent_app_number] => 8/937809
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[firstpage_image] =>[orig_patent_app_number] => 937809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937809 | Hardwire logic device emulating an FPGA | Sep 28, 1997 | Issued |
Array
(
[id] => 4101701
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[patent_title] => 'Apparatus and method for doubling speed of random events generator'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1997-09-23
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[pdf_file] => patents/06/163/06163874.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/935879 | Apparatus and method for doubling speed of random events generator | Sep 22, 1997 | Issued |
Array
(
[id] => 6893098
[patent_doc_number] => 20010015464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM'
[patent_app_type] => new
[patent_app_number] => 08/927069
[patent_app_country] => US
[patent_app_date] => 1997-09-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0015/20010015464.pdf
[firstpage_image] =>[orig_patent_app_number] => 08927069
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/927069 | Semiconductor integrated circuit, design method and computer-readable medium using a permissive current ratio | Sep 9, 1997 | Issued |
Array
(
[id] => 4293235
[patent_doc_number] => 06247164
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[patent_issue_date] => 2001-06-12
[patent_title] => 'Configurable hardware system implementing Boolean Satisfiability and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/919282
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919282 | Configurable hardware system implementing Boolean Satisfiability and method thereof | Aug 27, 1997 | Issued |
Array
(
[id] => 4271444
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[patent_issue_date] => 2001-04-24
[patent_title] => 'Pattern matching method, timing analysis method and timing analysis device'
[patent_app_type] => 1
[patent_app_number] => 8/882495
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[patent_app_date] => 1997-06-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882495 | Pattern matching method, timing analysis method and timing analysis device | Jun 24, 1997 | Issued |
Array
(
[id] => 4249113
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[patent_issue_date] => 2000-06-13
[patent_title] => 'Method for efficient implementation of multi-ported logic FIFO structures in a processor'
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[patent_app_number] => 8/882529
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Array
(
[id] => 4258479
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Array
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Array
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[patent_title] => 'Logic simulator which can maintain, store, and use historical event records'
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Array
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Array
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Array
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