Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4424813 [patent_doc_number] => 06266799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Multi-phase data/clock recovery circuitry and methods for implementing same' [patent_app_type] => 1 [patent_app_number] => 8/967087 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7443 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266799.pdf [firstpage_image] =>[orig_patent_app_number] => 967087 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967087
Multi-phase data/clock recovery circuitry and methods for implementing same Nov 9, 1997 Issued
Array ( [id] => 4311168 [patent_doc_number] => 06212669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for verifying and representing hardware by decomposition and partitioning' [patent_app_type] => 1 [patent_app_number] => 8/964904 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 13404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212669.pdf [firstpage_image] =>[orig_patent_app_number] => 964904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964904
Method for verifying and representing hardware by decomposition and partitioning Nov 4, 1997 Issued
08/960408 INTEGRATED CIRCUIT ASSEMBLY HAVING OUTPUT PADS WITH PROGRAMMABLE CHARACTERISTICS AND METHOD OF OPERATION Oct 28, 1997 Abandoned
Array ( [id] => 4099932 [patent_doc_number] => 06026226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Local compilation in context within a design hierarchy' [patent_app_type] => 1 [patent_app_number] => 8/958798 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10939 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026226.pdf [firstpage_image] =>[orig_patent_app_number] => 958798 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958798
Local compilation in context within a design hierarchy Oct 26, 1997 Issued
Array ( [id] => 4333930 [patent_doc_number] => 06317860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Electronic design automation tool for display of design profile' [patent_app_type] => 1 [patent_app_number] => 8/958431 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8335 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317860.pdf [firstpage_image] =>[orig_patent_app_number] => 958431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958431
Electronic design automation tool for display of design profile Oct 26, 1997 Issued
Array ( [id] => 3965582 [patent_doc_number] => 05991533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Verification support system' [patent_app_type] => 1 [patent_app_number] => 8/948992 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 64 [patent_no_of_words] => 16836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991533.pdf [firstpage_image] =>[orig_patent_app_number] => 948992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948992
Verification support system Oct 9, 1997 Issued
Array ( [id] => 4122661 [patent_doc_number] => 06120551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Hardwire logic device emulating an FPGA' [patent_app_type] => 1 [patent_app_number] => 8/937809 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13288 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/120/06120551.pdf [firstpage_image] =>[orig_patent_app_number] => 937809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937809
Hardwire logic device emulating an FPGA Sep 28, 1997 Issued
Array ( [id] => 4101701 [patent_doc_number] => 06163874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Apparatus and method for doubling speed of random events generator' [patent_app_type] => 1 [patent_app_number] => 8/935879 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 39 [patent_no_of_words] => 5422 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163874.pdf [firstpage_image] =>[orig_patent_app_number] => 935879 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935879
Apparatus and method for doubling speed of random events generator Sep 22, 1997 Issued
Array ( [id] => 6893098 [patent_doc_number] => 20010015464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM' [patent_app_type] => new [patent_app_number] => 08/927069 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10933 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015464.pdf [firstpage_image] =>[orig_patent_app_number] => 08927069 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927069
Semiconductor integrated circuit, design method and computer-readable medium using a permissive current ratio Sep 9, 1997 Issued
Array ( [id] => 4293235 [patent_doc_number] => 06247164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Configurable hardware system implementing Boolean Satisfiability and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/919282 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9763 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247164.pdf [firstpage_image] =>[orig_patent_app_number] => 919282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919282
Configurable hardware system implementing Boolean Satisfiability and method thereof Aug 27, 1997 Issued
Array ( [id] => 4271444 [patent_doc_number] => 06223333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Pattern matching method, timing analysis method and timing analysis device' [patent_app_type] => 1 [patent_app_number] => 8/882495 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223333.pdf [firstpage_image] =>[orig_patent_app_number] => 882495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882495
Pattern matching method, timing analysis method and timing analysis device Jun 24, 1997 Issued
Array ( [id] => 4249113 [patent_doc_number] => 06075931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for efficient implementation of multi-ported logic FIFO structures in a processor' [patent_app_type] => 1 [patent_app_number] => 8/882529 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4821 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075931.pdf [firstpage_image] =>[orig_patent_app_number] => 882529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882529
Method for efficient implementation of multi-ported logic FIFO structures in a processor Jun 24, 1997 Issued
Array ( [id] => 4258479 [patent_doc_number] => 06145115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Device for duplicating functions and a method for duplicating functions' [patent_app_type] => 1 [patent_app_number] => 8/879679 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8680 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145115.pdf [firstpage_image] =>[orig_patent_app_number] => 879679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879679
Device for duplicating functions and a method for duplicating functions Jun 22, 1997 Issued
Array ( [id] => 4291223 [patent_doc_number] => 06308305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method and apparatus for circuit designing of an LSI circuit without error paths' [patent_app_type] => 1 [patent_app_number] => 8/874506 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 15897 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308305.pdf [firstpage_image] =>[orig_patent_app_number] => 874506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874506
Method and apparatus for circuit designing of an LSI circuit without error paths Jun 12, 1997 Issued
Array ( [id] => 4421043 [patent_doc_number] => 06173241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Logic simulator which can maintain, store, and use historical event records' [patent_app_type] => 1 [patent_app_number] => 8/896509 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5613 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173241.pdf [firstpage_image] =>[orig_patent_app_number] => 896509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896509
Logic simulator which can maintain, store, and use historical event records Jun 9, 1997 Issued
Array ( [id] => 4207255 [patent_doc_number] => 06131182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros' [patent_app_type] => 1 [patent_app_number] => 8/850037 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7635 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131182.pdf [firstpage_image] =>[orig_patent_app_number] => 850037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850037
Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros May 1, 1997 Issued
Array ( [id] => 4147595 [patent_doc_number] => 06035106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and system for maintaining hierarchy throughout the integrated circuit design process' [patent_app_type] => 1 [patent_app_number] => 8/840338 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6113 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035106.pdf [firstpage_image] =>[orig_patent_app_number] => 840338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840338
Method and system for maintaining hierarchy throughout the integrated circuit design process Apr 27, 1997 Issued
Array ( [id] => 4147636 [patent_doc_number] => 06035109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method for using complete-1-distinguishability for FSM equivalence checking' [patent_app_type] => 1 [patent_app_number] => 8/847952 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7368 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035109.pdf [firstpage_image] =>[orig_patent_app_number] => 847952 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847952
Method for using complete-1-distinguishability for FSM equivalence checking Apr 21, 1997 Issued
Array ( [id] => 3918857 [patent_doc_number] => 05898862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Method for configuring an integrated circuit for emulation with optional on-chip emulation circuitry' [patent_app_type] => 1 [patent_app_number] => 8/840955 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4348 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898862.pdf [firstpage_image] =>[orig_patent_app_number] => 840955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840955
Method for configuring an integrated circuit for emulation with optional on-chip emulation circuitry Apr 20, 1997 Issued
Array ( [id] => 4129521 [patent_doc_number] => 06047117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Diffusion-based method and apparatus for determining circuit interconnect voltage response' [patent_app_type] => 1 [patent_app_number] => 8/838091 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3240 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047117.pdf [firstpage_image] =>[orig_patent_app_number] => 838091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838091
Diffusion-based method and apparatus for determining circuit interconnect voltage response Apr 14, 1997 Issued
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