
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
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[patent_issue_date] => 1999-11-16
[patent_title] => 'Computer system and method for building a hardware description language representation of control logic for a complex digital system'
[patent_app_type] => 1
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Array
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[patent_issue_date] => 1999-05-11
[patent_title] => 'Selecting phase assignments for candidate nodes in a logic network'
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Array
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[patent_issue_date] => 2000-02-15
[patent_title] => 'Design aiding apparatus and method for designing a semiconductor device'
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Array
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[patent_title] => 'Identifying candidate nodes for phase assignment in a logic network'
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[patent_title] => 'Identifying an optimizable logic region in a logic network'
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Array
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Array
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Array
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Array
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[patent_title] => 'Method and apparatus for intrusive testing of a microprocessor feature'
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Array
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Array
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Array
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Array
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Array
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Array
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