Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4016864 [patent_doc_number] => 05987239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Computer system and method for building a hardware description language representation of control logic for a complex digital system' [patent_app_type] => 1 [patent_app_number] => 8/766650 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4466 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987239.pdf [firstpage_image] =>[orig_patent_app_number] => 766650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766650
Computer system and method for building a hardware description language representation of control logic for a complex digital system Dec 12, 1996 Issued
Array ( [id] => 4038050 [patent_doc_number] => 05903467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Selecting phase assignments for candidate nodes in a logic network' [patent_app_type] => 1 [patent_app_number] => 8/763980 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5792 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903467.pdf [firstpage_image] =>[orig_patent_app_number] => 763980 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763980
Selecting phase assignments for candidate nodes in a logic network Dec 9, 1996 Issued
Array ( [id] => 4073067 [patent_doc_number] => 06024478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Design aiding apparatus and method for designing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/761901 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/024/06024478.pdf [firstpage_image] =>[orig_patent_app_number] => 761901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761901
Design aiding apparatus and method for designing a semiconductor device Dec 8, 1996 Issued
Array ( [id] => 4147650 [patent_doc_number] => 06035110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Identifying candidate nodes for phase assignment in a logic network' [patent_app_type] => 1 [patent_app_number] => 8/761890 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5781 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035110.pdf [firstpage_image] =>[orig_patent_app_number] => 761890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761890
Identifying candidate nodes for phase assignment in a logic network Dec 8, 1996 Issued
Array ( [id] => 4098326 [patent_doc_number] => 06018621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Identifying an optimizable logic region in a logic network' [patent_app_type] => 1 [patent_app_number] => 8/761891 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018621.pdf [firstpage_image] =>[orig_patent_app_number] => 761891 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761891
Identifying an optimizable logic region in a logic network Dec 8, 1996 Issued
Array ( [id] => 3965700 [patent_doc_number] => 05956496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Automated method for circuit optimization' [patent_app_type] => 1 [patent_app_number] => 8/761874 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6107 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956496.pdf [firstpage_image] =>[orig_patent_app_number] => 761874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761874
Automated method for circuit optimization Dec 8, 1996 Issued
Array ( [id] => 4212077 [patent_doc_number] => 06014505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Automated method for optimizing characteristics of electronic circuits' [patent_app_type] => 1 [patent_app_number] => 8/761873 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6744 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014505.pdf [firstpage_image] =>[orig_patent_app_number] => 761873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/761873
Automated method for optimizing characteristics of electronic circuits Dec 8, 1996 Issued
Array ( [id] => 4093277 [patent_doc_number] => 06099584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'System to fix post-layout timing and design rules violations' [patent_app_type] => 1 [patent_app_number] => 8/759711 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2754 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/099/06099584.pdf [firstpage_image] =>[orig_patent_app_number] => 759711 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759711
System to fix post-layout timing and design rules violations Dec 5, 1996 Issued
Array ( [id] => 4123646 [patent_doc_number] => 06058253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method and apparatus for intrusive testing of a microprocessor feature' [patent_app_type] => 1 [patent_app_number] => 8/760968 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7825 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058253.pdf [firstpage_image] =>[orig_patent_app_number] => 760968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760968
Method and apparatus for intrusive testing of a microprocessor feature Dec 4, 1996 Issued
Array ( [id] => 4054107 [patent_doc_number] => 05912819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method for designing an architectural system' [patent_app_type] => 1 [patent_app_number] => 8/758331 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4980 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912819.pdf [firstpage_image] =>[orig_patent_app_number] => 758331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758331
Method for designing an architectural system Dec 2, 1996 Issued
Array ( [id] => 4016836 [patent_doc_number] => 05987238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and system for simulating and making a phase lock loop circuit' [patent_app_type] => 1 [patent_app_number] => 8/756368 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6617 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987238.pdf [firstpage_image] =>[orig_patent_app_number] => 756368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756368
Method and system for simulating and making a phase lock loop circuit Nov 26, 1996 Issued
Array ( [id] => 4026682 [patent_doc_number] => 05880969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method and apparatus for deciding a wiring route and for detecting a critical cut' [patent_app_type] => 1 [patent_app_number] => 8/757718 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 11935 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880969.pdf [firstpage_image] =>[orig_patent_app_number] => 757718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757718
Method and apparatus for deciding a wiring route and for detecting a critical cut Nov 25, 1996 Issued
Array ( [id] => 3818322 [patent_doc_number] => 05854915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Keyboard controller with integrated real time clock functionality and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/755202 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854915.pdf [firstpage_image] =>[orig_patent_app_number] => 755202 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755202
Keyboard controller with integrated real time clock functionality and method therefor Nov 21, 1996 Issued
Array ( [id] => 4026984 [patent_doc_number] => 05907494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Computer system and method for performing design automation in a distributed computing environment' [patent_app_type] => 1 [patent_app_number] => 8/754142 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4465 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907494.pdf [firstpage_image] =>[orig_patent_app_number] => 754142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754142
Computer system and method for performing design automation in a distributed computing environment Nov 21, 1996 Issued
Array ( [id] => 4099905 [patent_doc_number] => 06026224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Redundant vias' [patent_app_type] => 1 [patent_app_number] => 8/753137 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4114 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026224.pdf [firstpage_image] =>[orig_patent_app_number] => 753137 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753137
Redundant vias Nov 19, 1996 Issued
Array ( [id] => 4235173 [patent_doc_number] => 06088523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and apparatus for simulating an electrical circuit design using approximate circuit element tapers' [patent_app_type] => 1 [patent_app_number] => 8/752812 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8093 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088523.pdf [firstpage_image] =>[orig_patent_app_number] => 752812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752812
Method and apparatus for simulating an electrical circuit design using approximate circuit element tapers Nov 19, 1996 Issued
Array ( [id] => 4049101 [patent_doc_number] => 05943486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Compaction method, compaction apparatus, routing method and routing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/752413 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 72 [patent_no_of_words] => 21836 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943486.pdf [firstpage_image] =>[orig_patent_app_number] => 752413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752413
Compaction method, compaction apparatus, routing method and routing apparatus Nov 18, 1996 Issued
Array ( [id] => 4099849 [patent_doc_number] => 06026220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method and apparatus for incremntally optimizing a circuit design' [patent_app_type] => 1 [patent_app_number] => 8/752617 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 10418 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026220.pdf [firstpage_image] =>[orig_patent_app_number] => 752617 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752617
Method and apparatus for incremntally optimizing a circuit design Nov 18, 1996 Issued
Array ( [id] => 4002695 [patent_doc_number] => 05960184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Method and apparatus for providing optimization parameters to a logic optimizer tool' [patent_app_type] => 1 [patent_app_number] => 8/752619 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8542 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960184.pdf [firstpage_image] =>[orig_patent_app_number] => 752619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752619
Method and apparatus for providing optimization parameters to a logic optimizer tool Nov 18, 1996 Issued
Array ( [id] => 3928837 [patent_doc_number] => 06002857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Symbolic constraint-based system for preroute reconstruction following floorplan incrementing' [patent_app_type] => 1 [patent_app_number] => 8/748764 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5313 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002857.pdf [firstpage_image] =>[orig_patent_app_number] => 748764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748764
Symbolic constraint-based system for preroute reconstruction following floorplan incrementing Nov 13, 1996 Issued
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