Jehanne Souaya Sitton

Array ( [id] => 11959714 [patent_doc_number] => 20170263866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/608959 [patent_app_country] => US [patent_app_date] => 2017-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11253 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15608959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11952355 [patent_doc_number] => 20170256506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/602290 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10667 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13630241 [patent_doc_number] => 20180366673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => QUANTUM DOT DISPLAY DEVICE AND MANUFACTURE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/571368 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11967143 [patent_doc_number] => 20170271296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'COATED BOND WIRES FOR DIE PACKAGES AND METHODS OF MANUFACTURING SAID COATED BOND WIRES' [patent_app_type] => utility [patent_app_number] => 15/597367 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3304 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946136 [patent_doc_number] => 20170250287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'BURIED SOURCE SCHOTTKY BARRIER THIN TRANSISTOR AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 15/597020 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4499 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15250349 [patent_doc_number] => 10510703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package [patent_app_type] => utility [patent_app_number] => 15/594443 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 35 [patent_no_of_words] => 13267 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11939793 [patent_doc_number] => 20170243942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/591405 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 19579 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11851458 [patent_doc_number] => 20170225950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'EMBEDDED STRUCTURES FOR HIGH GLASS STRENGTH AND ROBUST PACKAGING' [patent_app_type] => utility [patent_app_number] => 15/499381 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4056 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11854951 [patent_doc_number] => 20170229443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERTICAL GATE FIN-TYPE FIELD EFFECT DIODE' [patent_app_type] => utility [patent_app_number] => 15/497924 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12614787 [patent_doc_number] => 20180096759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => CHIP RESISTOR AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/558715 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15012103 [patent_doc_number] => 10452190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Array substrate and methods of manufacturing and driving the same [patent_app_type] => utility [patent_app_number] => 15/484259 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5001 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11824953 [patent_doc_number] => 20170213890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 15/482086 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4981 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15234605 [patent_doc_number] => 10505033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Electronic device of vertical MOS type with termination trenches having variable depth [patent_app_type] => utility [patent_app_number] => 15/479975 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 47 [patent_no_of_words] => 11225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13667807 [patent_doc_number] => 10164085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Apparatus and method for power MOS transistor [patent_app_type] => utility [patent_app_number] => 15/464423 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15464423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710840 [patent_doc_number] => 20170179339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Display Light Sources With Quantum Dots' [patent_app_type] => utility [patent_app_number] => 15/452294 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11869595 [patent_doc_number] => 20170236880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/423150 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13388 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14252361 [patent_doc_number] => 10276387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Semiconductor device including superjunction structure formed using angled implant process [patent_app_type] => utility [patent_app_number] => 15/423154 [patent_app_country] => US [patent_app_date] => 2017-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6019 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14064213 [patent_doc_number] => 10236413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Light-emitting device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/412759 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 9101 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11608243 [patent_doc_number] => 20170125547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'METHOD OF FORMING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/406355 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12175003 [patent_doc_number] => 09893151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method and apparatus providing improved thermal conductivity of strain relaxed buffer' [patent_app_type] => utility [patent_app_number] => 15/404301 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4438 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404301 [rel_patent_id] =>[rel_patent_doc_number] =>)