Search

Jennifer M. Dolan

Examiner (ID: 4568)

Most Active Art Unit
2813
Art Unit(s)
2813, 2652
Total Applications
367
Issued Applications
294
Pending Applications
9
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7383508 [patent_doc_number] => 20040082174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad' [patent_app_type] => new [patent_app_number] => 10/689026 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1295 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082174.pdf [firstpage_image] =>[orig_patent_app_number] => 10689026 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689026
Method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad Oct 20, 2003 Abandoned
Array ( [id] => 7383269 [patent_doc_number] => 20040082134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method for using thin spacers and oxidation in gate oxides' [patent_app_type] => new [patent_app_number] => 10/690200 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4361 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082134.pdf [firstpage_image] =>[orig_patent_app_number] => 10690200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690200
Method for using thin spacers and oxidation in gate oxides Oct 20, 2003 Abandoned
Array ( [id] => 7616732 [patent_doc_number] => 06946710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method and structure to reduce CMOS inter-well leakage' [patent_app_type] => utility [patent_app_number] => 10/687295 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 4653 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946710.pdf [firstpage_image] =>[orig_patent_app_number] => 10687295 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687295
Method and structure to reduce CMOS inter-well leakage Oct 15, 2003 Issued
Array ( [id] => 766153 [patent_doc_number] => 07008807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Manufacturing method of electro-optical device substrate and manufacturing method of electro-optical device' [patent_app_type] => utility [patent_app_number] => 10/683166 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 11775 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/008/07008807.pdf [firstpage_image] =>[orig_patent_app_number] => 10683166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683166
Manufacturing method of electro-optical device substrate and manufacturing method of electro-optical device Oct 9, 2003 Issued
Array ( [id] => 993954 [patent_doc_number] => 06917054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/681126 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3326 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917054.pdf [firstpage_image] =>[orig_patent_app_number] => 10681126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681126
Semiconductor device Oct 8, 2003 Issued
Array ( [id] => 756336 [patent_doc_number] => 07019384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Integrated, tunable capacitance device' [patent_app_type] => utility [patent_app_number] => 10/678385 [patent_app_country] => US [patent_app_date] => 2003-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5253 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/019/07019384.pdf [firstpage_image] =>[orig_patent_app_number] => 10678385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678385
Integrated, tunable capacitance device Oct 2, 2003 Issued
Array ( [id] => 650939 [patent_doc_number] => 07112516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Fabrication of abrupt ultra-shallow junctions' [patent_app_type] => utility [patent_app_number] => 10/677614 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3911 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112516.pdf [firstpage_image] =>[orig_patent_app_number] => 10677614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677614
Fabrication of abrupt ultra-shallow junctions Oct 1, 2003 Issued
Array ( [id] => 953834 [patent_doc_number] => 06958247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process' [patent_app_type] => utility [patent_app_number] => 10/666195 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6069 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958247.pdf [firstpage_image] =>[orig_patent_app_number] => 10666195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666195
Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process Sep 18, 2003 Issued
Array ( [id] => 687779 [patent_doc_number] => 07078771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'SOI structure and method of producing same' [patent_app_type] => utility [patent_app_number] => 10/666865 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4401 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078771.pdf [firstpage_image] =>[orig_patent_app_number] => 10666865 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666865
SOI structure and method of producing same Sep 17, 2003 Issued
Array ( [id] => 938657 [patent_doc_number] => 06972486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Low profile carrier for non-wafer form device testing' [patent_app_type] => utility [patent_app_number] => 10/661316 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2962 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972486.pdf [firstpage_image] =>[orig_patent_app_number] => 10661316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/661316
Low profile carrier for non-wafer form device testing Sep 11, 2003 Issued
Array ( [id] => 641692 [patent_doc_number] => 07122391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Wafer-level test structure for edge-emitting semiconductor lasers' [patent_app_type] => utility [patent_app_number] => 10/659898 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3677 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122391.pdf [firstpage_image] =>[orig_patent_app_number] => 10659898 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659898
Wafer-level test structure for edge-emitting semiconductor lasers Sep 10, 2003 Issued
Array ( [id] => 7198381 [patent_doc_number] => 20050051820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Fabrication process for a magnetic tunnel junction device' [patent_app_type] => utility [patent_app_number] => 10/659136 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9362 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051820.pdf [firstpage_image] =>[orig_patent_app_number] => 10659136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/659136
Fabrication process for a magnetic tunnel junction device Sep 9, 2003 Issued
Array ( [id] => 982596 [patent_doc_number] => 06927440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Metal-insulator-metal capacitor' [patent_app_type] => utility [patent_app_number] => 10/658036 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2717 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927440.pdf [firstpage_image] =>[orig_patent_app_number] => 10658036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658036
Metal-insulator-metal capacitor Sep 8, 2003 Issued
Array ( [id] => 968541 [patent_doc_number] => 06939815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Method for making a semiconductor device having a high-k gate dielectric' [patent_app_type] => utility [patent_app_number] => 10/652796 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3162 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939815.pdf [firstpage_image] =>[orig_patent_app_number] => 10652796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652796
Method for making a semiconductor device having a high-k gate dielectric Aug 27, 2003 Issued
Array ( [id] => 7380286 [patent_doc_number] => 20040036147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Semiconductor chip having an arrayed waveguide grating and method of manufacturing the semiconductor chip and module containing the semiconductor chip' [patent_app_type] => new [patent_app_number] => 10/648276 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5343 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036147.pdf [firstpage_image] =>[orig_patent_app_number] => 10648276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648276
Semiconductor chip having an arrayed waveguide grating and method of manufacturing the semiconductor chip and module containing the semiconductor chip Aug 26, 2003 Abandoned
Array ( [id] => 7083415 [patent_doc_number] => 20050048795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method for ultra low-K dielectric deposition' [patent_app_type] => utility [patent_app_number] => 10/649566 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1829 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048795.pdf [firstpage_image] =>[orig_patent_app_number] => 10649566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649566
Method for ultra low-K dielectric deposition Aug 26, 2003 Abandoned
Array ( [id] => 7260271 [patent_doc_number] => 20040150074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Anti-reflective coating (ARC) material, semiconductor product with an ARC layer and method of coating a semiconductor product with an ARC layer' [patent_app_type] => new [patent_app_number] => 10/646206 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2876 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150074.pdf [firstpage_image] =>[orig_patent_app_number] => 10646206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646206
Anti-reflective coating (ARC) material, semiconductor product with an ARC layer and method of coating a semiconductor product with an ARC layer Aug 21, 2003 Abandoned
Array ( [id] => 606359 [patent_doc_number] => 07153724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Method of fabricating no-lead package for semiconductor die with half-etched leadframe' [patent_app_type] => utility [patent_app_number] => 10/637965 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 3922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/153/07153724.pdf [firstpage_image] =>[orig_patent_app_number] => 10637965 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637965
Method of fabricating no-lead package for semiconductor die with half-etched leadframe Aug 7, 2003 Issued
Array ( [id] => 672113 [patent_doc_number] => 07091125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method and apparatus for structuring electrodes for organic light-emitting display and organic light-emitting display manufactured using the method and apparatus' [patent_app_type] => utility [patent_app_number] => 10/635484 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2802 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091125.pdf [firstpage_image] =>[orig_patent_app_number] => 10635484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635484
Method and apparatus for structuring electrodes for organic light-emitting display and organic light-emitting display manufactured using the method and apparatus Aug 6, 2003 Issued
Array ( [id] => 982622 [patent_doc_number] => 06927466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication' [patent_app_type] => utility [patent_app_number] => 10/633628 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 4975 [patent_no_of_claims] => 92 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927466.pdf [firstpage_image] =>[orig_patent_app_number] => 10633628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633628
Magnetoresistive memory or sensor devices having improved switching properties and method of fabrication Aug 4, 2003 Issued
Menu