Search

Jennifer Mehmood

Supervisory Patent Examiner (ID: 15735, Phone: (571)272-2976 , Office: P/2627 )

Most Active Art Unit
2612
Art Unit(s)
2627, 2600, 2636, 2612, 2689, 2664, 2681
Total Applications
624
Issued Applications
422
Pending Applications
34
Abandoned Applications
168

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19144616 [patent_doc_number] => 20240143533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => TOKENIZATION SYSTEM WITH COMMON BUS ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/373391 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373391
Tokenization system with common bus architecture Sep 26, 2023 Issued
Array ( [id] => 19748012 [patent_doc_number] => 20250036577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SYSTEM AND METHOD TO FACILITATE ACCESS BY A REMOTE COMPUTER TO A PCIE CONFIGURATION SPACE [patent_app_type] => utility [patent_app_number] => 18/470051 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470051 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470051
System and method to facilitate access by a remote computer to a PCIe configuration space Sep 18, 2023 Issued
Array ( [id] => 20145701 [patent_doc_number] => 12380044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor device, bus control circuit and bus control method [patent_app_type] => utility [patent_app_number] => 18/468032 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4608 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468032 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/468032
Semiconductor device, bus control circuit and bus control method Sep 14, 2023 Issued
Array ( [id] => 20564110 [patent_doc_number] => 12566720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Integrated circuit, chip, and electronic device [patent_app_type] => utility [patent_app_number] => 18/467379 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/467379
Integrated circuit, chip, and electronic device Sep 13, 2023 Issued
Array ( [id] => 19802656 [patent_doc_number] => 20250068581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => Passive Clock Synchronization For Timing [patent_app_type] => utility [patent_app_number] => 18/237171 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237171 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237171
Passive clock synchronization for timing Aug 22, 2023 Issued
Array ( [id] => 18819660 [patent_doc_number] => 20230394000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => INTERCONNECTION SYSTEM, DATA TRANSMISSION METHOD, AND CHIP [patent_app_type] => utility [patent_app_number] => 18/453733 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453733
INTERCONNECTION SYSTEM, DATA TRANSMISSION METHOD, AND CHIP Aug 21, 2023 Pending
Array ( [id] => 18957486 [patent_doc_number] => 20240045813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY [patent_app_type] => utility [patent_app_number] => 18/236272 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236272
Training and operations with a double buffered memory topology Aug 20, 2023 Issued
Array ( [id] => 19828067 [patent_doc_number] => 12248851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-11 [patent_title] => Thermalization and attenuation of signals within quantum computing systems via directional couplers [patent_app_type] => utility [patent_app_number] => 18/450996 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450996 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450996
Thermalization and attenuation of signals within quantum computing systems via directional couplers Aug 15, 2023 Issued
Array ( [id] => 19911539 [patent_doc_number] => 12287748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection [patent_app_type] => utility [patent_app_number] => 18/446501 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446501
High-speed low-latency interconnect interface (HLII) for silicon interposer interconnection Aug 8, 2023 Issued
Array ( [id] => 19857009 [patent_doc_number] => 12259845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Managing communications between chassis [patent_app_type] => utility [patent_app_number] => 18/230884 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6067 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230884
Managing communications between chassis Aug 6, 2023 Issued
Array ( [id] => 19911537 [patent_doc_number] => 12287746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Management of endpoint devices utilizing tag bridge devices [patent_app_type] => utility [patent_app_number] => 18/366019 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366019 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366019
Management of endpoint devices utilizing tag bridge devices Aug 6, 2023 Issued
Array ( [id] => 18881050 [patent_doc_number] => 20240004419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory [patent_app_type] => utility [patent_app_number] => 18/230418 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230418
Computer architecture having selectable parallel and serial communication channels between processors and memory Aug 3, 2023 Issued
Array ( [id] => 18941730 [patent_doc_number] => 20240036869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => HARDWARE STATE REPORTING USING INTERRUPT PINS [patent_app_type] => utility [patent_app_number] => 18/221230 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221230 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221230
Hardware state reporting using interrupt pins Jul 11, 2023 Issued
Array ( [id] => 18881456 [patent_doc_number] => 20240004825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SERIAL DAISY-CHAINED BUS POWER FOR SERIAL DAISY-CHAINED COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/346214 [patent_app_country] => US [patent_app_date] => 2023-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346214
Serial daisy-chained bus power for serial daisy-chained communication system Jun 30, 2023 Issued
Array ( [id] => 18714166 [patent_doc_number] => 20230336806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DISPLAY APPARATUS AND PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 18/340512 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340512
Display apparatus and processing method Jun 22, 2023 Issued
Array ( [id] => 19660649 [patent_doc_number] => 20240427714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND IMPROVING PERFORMANCE IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/338070 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338070
Systems and methods for reducing latency and improving performance in a peripheral component interconnect express (PCIe) system Jun 19, 2023 Issued
Array ( [id] => 19645093 [patent_doc_number] => 20240419613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SYSTEMS AND METHODS FOR REDUCING LATENCY AND POWER CONSUMPTION IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SYSTEM [patent_app_type] => utility [patent_app_number] => 18/337235 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337235 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337235
Systems and methods for reducing latency and power consumption in a peripheral component interconnect express (PCIe) system Jun 18, 2023 Issued
Array ( [id] => 18847104 [patent_doc_number] => 20230409508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DATA FLOW MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/211180 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211180
Data flow management Jun 15, 2023 Issued
Array ( [id] => 19609979 [patent_doc_number] => 12158853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Method for data access control among multiple nodes and data access system [patent_app_type] => utility [patent_app_number] => 18/325124 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4005 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325124
Method for data access control among multiple nodes and data access system May 29, 2023 Issued
Array ( [id] => 18877824 [patent_doc_number] => 20240001193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SYSTEM AND METHOD FOR TARGETED NEUROLOGICAL THERAPY USING BRAINWAVE ENTRAINMENT WITH PASSIVE TREATMENT [patent_app_type] => utility [patent_app_number] => 18/322593 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322593 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322593
System and method for targeted neurological therapy using brainwave entrainment with passive treatment May 23, 2023 Issued
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