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Jennifer Wecker

Examiner (ID: 3547, Phone: (571)270-1109 , Office: P/1797 )

Most Active Art Unit
1797
Art Unit(s)
1797, 1779, 1772, 4172
Total Applications
999
Issued Applications
754
Pending Applications
57
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3561192 [patent_doc_number] => 05546553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Multifunctional access devices, systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/359324 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 89 [patent_no_of_words] => 35960 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546553.pdf [firstpage_image] =>[orig_patent_app_number] => 359324 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/359324
Multifunctional access devices, systems and methods Dec 14, 1994 Issued
Array ( [id] => 3521668 [patent_doc_number] => 05588130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Semiconductor memory device for simple cache system' [patent_app_type] => 1 [patent_app_number] => 8/283367 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9158 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/588/05588130.pdf [firstpage_image] =>[orig_patent_app_number] => 283367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283367
Semiconductor memory device for simple cache system Jul 31, 1994 Issued
Array ( [id] => 3532246 [patent_doc_number] => 05530834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Set-associative cache memory having an enhanced LRU replacement strategy' [patent_app_type] => 1 [patent_app_number] => 8/206001 [patent_app_country] => US [patent_app_date] => 1994-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2641 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530834.pdf [firstpage_image] =>[orig_patent_app_number] => 206001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/206001
Set-associative cache memory having an enhanced LRU replacement strategy Mar 2, 1994 Issued
Array ( [id] => 3561215 [patent_doc_number] => 05546554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Apparatus for dynamic register management in a floating point unit' [patent_app_type] => 1 [patent_app_number] => 8/190872 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 7658 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546554.pdf [firstpage_image] =>[orig_patent_app_number] => 190872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/190872
Apparatus for dynamic register management in a floating point unit Feb 1, 1994 Issued
Array ( [id] => 3600053 [patent_doc_number] => 05553257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Address generating circuit of a two-dimensional coding table' [patent_app_type] => 1 [patent_app_number] => 8/189680 [patent_app_country] => US [patent_app_date] => 1994-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5160 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553257.pdf [firstpage_image] =>[orig_patent_app_number] => 189680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/189680
Address generating circuit of a two-dimensional coding table Jan 31, 1994 Issued
08/173588 SYSTEM AND METHOD FOR SKIP-SECTOR MAPPING IN A DATA RECORDING DISK DRIVE Dec 22, 1993 Abandoned
Array ( [id] => 3625694 [patent_doc_number] => 05566321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Method of managing distributed memory within a massively parallel processing system' [patent_app_type] => 1 [patent_app_number] => 8/166293 [patent_app_country] => US [patent_app_date] => 1993-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3152 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566321.pdf [firstpage_image] =>[orig_patent_app_number] => 166293 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166293
Method of managing distributed memory within a massively parallel processing system Dec 12, 1993 Issued
08/150850 MEMORY CONTROLLER WITH BURST ADDRESSING CIRCUIT Nov 11, 1993 Abandoned
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