
Jenny L. Wagner
Supervisory Patent Examiner (ID: 9505, Phone: (571)272-5359 , Office: P/2848 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, 2848, 2112, 2800 |
| Total Applications | 432 |
| Issued Applications | 298 |
| Pending Applications | 0 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5141870
[patent_doc_number] => 20070004086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same'
[patent_app_type] => utility
[patent_app_number] => 11/173238
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7034
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20070004086.pdf
[firstpage_image] =>[orig_patent_app_number] => 11173238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/173238 | Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same | Jun 29, 2005 | Issued |
Array
(
[id] => 6975525
[patent_doc_number] => 20050285240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/167169
[patent_app_country] => US
[patent_app_date] => 2005-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4081
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20050285240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11167169
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/167169 | Semiconductor device and method of manufacturing the same | Jun 27, 2005 | Issued |
Array
(
[id] => 6978074
[patent_doc_number] => 20050287792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Method for forming barrier layer of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/166678
[patent_app_country] => US
[patent_app_date] => 2005-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2404
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0287/20050287792.pdf
[firstpage_image] =>[orig_patent_app_number] => 11166678
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/166678 | Method for forming barrier layer of semiconductor device | Jun 22, 2005 | Abandoned |
Array
(
[id] => 393929
[patent_doc_number] => 07297622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Wiring method'
[patent_app_type] => utility
[patent_app_number] => 11/156578
[patent_app_country] => US
[patent_app_date] => 2005-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 9635
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/297/07297622.pdf
[firstpage_image] =>[orig_patent_app_number] => 11156578
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/156578 | Wiring method | Jun 20, 2005 | Issued |
Array
(
[id] => 820912
[patent_doc_number] => 07408246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-05
[patent_title] => 'Controlling warping in integrated circuit devices'
[patent_app_type] => utility
[patent_app_number] => 11/095929
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 4343
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/408/07408246.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095929
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095929 | Controlling warping in integrated circuit devices | Mar 30, 2005 | Issued |
Array
(
[id] => 7136903
[patent_doc_number] => 20050181580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Method for manufacturing mesa semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/057188
[patent_app_country] => US
[patent_app_date] => 2005-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3119
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20050181580.pdf
[firstpage_image] =>[orig_patent_app_number] => 11057188
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/057188 | Method for manufacturing mesa semiconductor device | Feb 14, 2005 | Issued |
Array
(
[id] => 7050808
[patent_doc_number] => 20050186695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Method for manufacturing solid-state imaging device'
[patent_app_type] => utility
[patent_app_number] => 11/049029
[patent_app_country] => US
[patent_app_date] => 2005-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7880
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20050186695.pdf
[firstpage_image] =>[orig_patent_app_number] => 11049029
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/049029 | Method for manufacturing solid-state imaging device | Jan 31, 2005 | Abandoned |
Array
(
[id] => 5667118
[patent_doc_number] => 20060172468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Method of making a planar double-gated transistor'
[patent_app_type] => utility
[patent_app_number] => 11/047448
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3151
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20060172468.pdf
[firstpage_image] =>[orig_patent_app_number] => 11047448
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/047448 | Method of making a planar double-gated transistor | Jan 30, 2005 | Issued |
Array
(
[id] => 5667146
[patent_doc_number] => 20060172496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS)'
[patent_app_type] => utility
[patent_app_number] => 10/905979
[patent_app_country] => US
[patent_app_date] => 2005-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2637
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20060172496.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905979 | Double-gate FETs (Field Effect Transistors) | Jan 27, 2005 | Issued |
Array
(
[id] => 260412
[patent_doc_number] => 07573141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Semiconductor package with a chip on a support plate'
[patent_app_type] => utility
[patent_app_number] => 10/961466
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1580
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/573/07573141.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961466
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961466 | Semiconductor package with a chip on a support plate | Oct 7, 2004 | Issued |
Array
(
[id] => 849524
[patent_doc_number] => 07382043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-03
[patent_title] => 'Method and apparatus for shielding an integrated circuit from radiation'
[patent_app_type] => utility
[patent_app_number] => 10/065209
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5137
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/382/07382043.pdf
[firstpage_image] =>[orig_patent_app_number] => 10065209
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/065209 | Method and apparatus for shielding an integrated circuit from radiation | Sep 24, 2002 | Issued |
Array
(
[id] => 1505727
[patent_doc_number] => 06465961
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Semiconductor light source using a heat sink with a plurality of panels'
[patent_app_type] => B1
[patent_app_number] => 09/939340
[patent_app_country] => US
[patent_app_date] => 2001-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 24
[patent_no_of_words] => 5517
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/465/06465961.pdf
[firstpage_image] =>[orig_patent_app_number] => 09939340
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/939340 | Semiconductor light source using a heat sink with a plurality of panels | Aug 23, 2001 | Issued |