Search

Jenny L. Wagner

Supervisory Patent Examiner (ID: 7394, Phone: (571)272-5359 , Office: P/2848 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2848, 2112, 2800
Total Applications
432
Issued Applications
298
Pending Applications
0
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8897251 [patent_doc_number] => 08476774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Off-chip VIAS in stacked chips' [patent_app_type] => utility [patent_app_number] => 13/316890 [patent_app_country] => US [patent_app_date] => 2011-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6809 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 453 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316890
Off-chip VIAS in stacked chips Dec 11, 2011 Issued
Array ( [id] => 9039873 [patent_doc_number] => 20130242511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'WIRING BOARD, DISPLAY PANEL, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/883197 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6466 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/883197
WIRING BOARD, DISPLAY PANEL, AND ELECTRONIC APPARATUS Nov 9, 2011 Abandoned
Array ( [id] => 8172644 [patent_doc_number] => 20120108014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/288207 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 29307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20120108014.pdf [firstpage_image] =>[orig_patent_app_number] => 13288207 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/288207
Method for manufacturing semiconductor device Nov 2, 2011 Issued
Array ( [id] => 9697891 [patent_doc_number] => 20140247576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'HIGH-VOLTAGE PLATFORM' [patent_app_type] => utility [patent_app_number] => 14/355332 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1363 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14355332 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/355332
HIGH-VOLTAGE PLATFORM Oct 30, 2011 Abandoned
Array ( [id] => 8765057 [patent_doc_number] => 20130093094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Method and Apparatus for Die Assembly' [patent_app_type] => utility [patent_app_number] => 13/276184 [patent_app_country] => US [patent_app_date] => 2011-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276184 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276184
Method and apparatus for die assembly Oct 17, 2011 Issued
Array ( [id] => 9074991 [patent_doc_number] => 08552571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Electronic device and method for production' [patent_app_type] => utility [patent_app_number] => 13/267385 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7806 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267385 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/267385
Electronic device and method for production Oct 5, 2011 Issued
Array ( [id] => 8544059 [patent_doc_number] => 08319353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-27 [patent_title] => 'Pre-formed conductive bumps on bonding pads' [patent_app_type] => utility [patent_app_number] => 13/246979 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3405 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13246979 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/246979
Pre-formed conductive bumps on bonding pads Sep 27, 2011 Issued
Array ( [id] => 7738862 [patent_doc_number] => 20120018838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'METHOD FOR MODULAR ARRANGEMENT OF A SILICON BASED ARRAY AND MODULAR SILICON BASED ARRAY' [patent_app_type] => utility [patent_app_number] => 13/246170 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6128 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20120018838.pdf [firstpage_image] =>[orig_patent_app_number] => 13246170 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/246170
Method for modular arrangement of a silicon based array and modular silicon based array Sep 26, 2011 Issued
Array ( [id] => 9167308 [patent_doc_number] => 08592991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/235369 [patent_app_country] => US [patent_app_date] => 2011-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10926 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/235369
Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device Sep 16, 2011 Issued
Array ( [id] => 8090963 [patent_doc_number] => 20120081089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'POWER SUPPLY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/230911 [patent_app_country] => US [patent_app_date] => 2011-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3538 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20120081089.pdf [firstpage_image] =>[orig_patent_app_number] => 13230911 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/230911
POWER SUPPLY CIRCUIT Sep 12, 2011 Abandoned
Array ( [id] => 7669610 [patent_doc_number] => 20110318879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/228615 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8118 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228615 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228615
METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE Sep 8, 2011 Abandoned
Array ( [id] => 7815191 [patent_doc_number] => 20120061811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES' [patent_app_type] => utility [patent_app_number] => 13/228153 [patent_app_country] => US [patent_app_date] => 2011-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4184 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061811.pdf [firstpage_image] =>[orig_patent_app_number] => 13228153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228153
Apparatus and method configured to lower thermal stresses Sep 7, 2011 Issued
Array ( [id] => 7662840 [patent_doc_number] => 20110312109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'LIGHT EMITTING DIODE PACKAGE HAVING ANODIZED INSULATION LAYER AND FABRICATION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/220258 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3440 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20110312109.pdf [firstpage_image] =>[orig_patent_app_number] => 13220258 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/220258
Light emitting diode package having anodized insulation layer and fabrication method therefor Aug 28, 2011 Issued
Array ( [id] => 7662860 [patent_doc_number] => 20110312129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES' [patent_app_type] => utility [patent_app_number] => 13/219801 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20110312129.pdf [firstpage_image] =>[orig_patent_app_number] => 13219801 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219801
Interconnection in multi-chip with interposers and bridges Aug 28, 2011 Issued
Array ( [id] => 9167226 [patent_doc_number] => 08592909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Transistor including single layer reentrant profile' [patent_app_type] => utility [patent_app_number] => 13/218482 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4843 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/218482
Transistor including single layer reentrant profile Aug 25, 2011 Issued
Array ( [id] => 8658191 [patent_doc_number] => 20130039020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'PASSENGER SERVICE UNIT' [patent_app_type] => utility [patent_app_number] => 13/208580 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3404 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/208580
PASSENGER SERVICE UNIT Aug 11, 2011 Abandoned
Array ( [id] => 8657120 [patent_doc_number] => 20130037949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED METHODS OF MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 13/206321 [patent_app_country] => US [patent_app_date] => 2011-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2769 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13206321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/206321
Semiconductor assemblies with multi-level substrates and associated methods of manufacturing Aug 8, 2011 Issued
Array ( [id] => 8634832 [patent_doc_number] => 20130026635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'Hybrid Copper Interconnect Structure and Method of Fabricating Same' [patent_app_type] => utility [patent_app_number] => 13/191999 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13191999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/191999
Hybrid copper interconnect structure and method of fabricating same Jul 26, 2011 Issued
Array ( [id] => 9074987 [patent_doc_number] => 08552567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication' [patent_app_type] => utility [patent_app_number] => 13/192014 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 6504 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192014 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192014
Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication Jul 26, 2011 Issued
Array ( [id] => 8834433 [patent_doc_number] => 08450189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Film for flip chip type semiconductor back surface' [patent_app_type] => utility [patent_app_number] => 13/192068 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 19436 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192068 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192068
Film for flip chip type semiconductor back surface Jul 26, 2011 Issued
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