Search

Jenny L. Wagner

Supervisory Patent Examiner (ID: 9120, Phone: (571)272-5359 , Office: P/2848 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2848, 2800, 2112
Total Applications
432
Issued Applications
298
Pending Applications
0
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9286132 [patent_doc_number] => 08642461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Side wettable plating for semiconductor chip package' [patent_app_type] => utility [patent_app_number] => 13/189857 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7024 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189857 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189857
Side wettable plating for semiconductor chip package Jul 24, 2011 Issued
Array ( [id] => 9127796 [patent_doc_number] => 08575747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Clip interconnect with encapsulation material locking feature' [patent_app_type] => utility [patent_app_number] => 13/189074 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4088 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189074
Clip interconnect with encapsulation material locking feature Jul 21, 2011 Issued
Array ( [id] => 8615390 [patent_doc_number] => 20130020702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'DOUBLE-SIDED FLIP CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/188287 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188287 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188287
DOUBLE-SIDED FLIP CHIP PACKAGE Jul 20, 2011 Abandoned
Array ( [id] => 8926637 [patent_doc_number] => 20130182397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'Circuit Board Structure Used for Vehicle-Mounted Electronic Device' [patent_app_type] => utility [patent_app_number] => 13/812141 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5485 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13812141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/812141
Circuit Board Structure Used for Vehicle-Mounted Electronic Device Jul 19, 2011 Abandoned
Array ( [id] => 8582147 [patent_doc_number] => 20130000968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => '1-Layer Interposer Substrate With Through-Substrate Posts' [patent_app_type] => utility [patent_app_number] => 13/173689 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3963 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173689 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173689
1-Layer Interposer Substrate With Through-Substrate Posts Jun 29, 2011 Abandoned
Array ( [id] => 7801531 [patent_doc_number] => 08129804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Electronic device, resonator, oscillator and method for manufacturing electronic device' [patent_app_type] => utility [patent_app_number] => 13/168561 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 12485 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129804.pdf [firstpage_image] =>[orig_patent_app_number] => 13168561 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/168561
Electronic device, resonator, oscillator and method for manufacturing electronic device Jun 23, 2011 Issued
Array ( [id] => 8918833 [patent_doc_number] => RE044376 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2013-07-16 [patent_title] => 'Silicon substrate with reduced surface roughness' [patent_app_type] => reissue [patent_app_number] => 13/117881 [patent_app_country] => US [patent_app_date] => 2011-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2902 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13117881 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/117881
Silicon substrate with reduced surface roughness May 26, 2011 Issued
Array ( [id] => 9216256 [patent_doc_number] => 08629056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections' [patent_app_type] => utility [patent_app_number] => 13/107549 [patent_app_country] => US [patent_app_date] => 2011-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13107549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/107549
Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections May 12, 2011 Issued
Array ( [id] => 8706628 [patent_doc_number] => 20130063917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'PRINTED CIRCUIT BOARD INCLUDING UNDER-FILL DAM AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/699275 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8538 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13699275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/699275
Printed circuit board including under-fill dam and fabrication method thereof May 10, 2011 Issued
Array ( [id] => 8766130 [patent_doc_number] => 20130094166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/701541 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13701541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/701541
DISPLAY APPARATUS May 10, 2011 Abandoned
Array ( [id] => 5932587 [patent_doc_number] => 20110210451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHODS OF FORMING A METAL PATTERN AND SEMICONDUCTOR DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/104215 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5796 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210451.pdf [firstpage_image] =>[orig_patent_app_number] => 13104215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104215
Methods of forming a metal pattern and semiconductor device structure May 9, 2011 Issued
Array ( [id] => 6042409 [patent_doc_number] => 20110204486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 13/098648 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17294 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204486.pdf [firstpage_image] =>[orig_patent_app_number] => 13098648 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098648
Method of manufacturing a semiconductor integrated circuit device May 1, 2011 Issued
Array ( [id] => 8317874 [patent_doc_number] => 08232654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same' [patent_app_type] => utility [patent_app_number] => 13/089666 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9878 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089666
Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same Apr 18, 2011 Issued
Array ( [id] => 6106185 [patent_doc_number] => 20110187007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'EDGE CONNECT WAFER LEVEL STACKING' [patent_app_type] => utility [patent_app_number] => 13/086645 [patent_app_country] => US [patent_app_date] => 2011-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10988 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20110187007.pdf [firstpage_image] =>[orig_patent_app_number] => 13086645 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/086645
Edge connect wafer level stacking Apr 13, 2011 Issued
Array ( [id] => 6106173 [patent_doc_number] => 20110186995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'SOLDER BUMP INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 13/085759 [patent_app_country] => US [patent_app_date] => 2011-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186995.pdf [firstpage_image] =>[orig_patent_app_number] => 13085759 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/085759
Solder bump interconnect Apr 12, 2011 Issued
Array ( [id] => 5955830 [patent_doc_number] => 20110180877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/081208 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 20952 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20110180877.pdf [firstpage_image] =>[orig_patent_app_number] => 13081208 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/081208
Semiconductor device and a method of manufacturing the same Apr 5, 2011 Issued
Array ( [id] => 6106105 [patent_doc_number] => 20110186943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'MEMS Package and Method for the Production Thereof' [patent_app_type] => utility [patent_app_number] => 13/075936 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7399 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186943.pdf [firstpage_image] =>[orig_patent_app_number] => 13075936 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075936
MEMS package and method for the production thereof Mar 29, 2011 Issued
Array ( [id] => 8093133 [patent_doc_number] => 20120082176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'CONDUCTION COOLED PACKAGE LASER AND PACKAGING METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/072793 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2830 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20120082176.pdf [firstpage_image] =>[orig_patent_app_number] => 13072793 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/072793
CONDUCTION COOLED PACKAGE LASER AND PACKAGING METHOD FOR FORMING THE SAME Mar 27, 2011 Abandoned
Array ( [id] => 8605130 [patent_doc_number] => 20130010442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'CIRCUIT ARRANGEMENT AND ASSOCIATED CONTROLLER FOR A MOTOR VEHICLE' [patent_app_type] => utility [patent_app_number] => 13/635093 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3542 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/635093
CIRCUIT ARRANGEMENT AND ASSOCIATED CONTROLLER FOR A MOTOR VEHICLE Mar 10, 2011 Abandoned
Array ( [id] => 6183380 [patent_doc_number] => 20110168564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'PLATING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD AND CIRCUIT BOARD FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/043854 [patent_app_country] => US [patent_app_date] => 2011-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 24246 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20110168564.pdf [firstpage_image] =>[orig_patent_app_number] => 13043854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/043854
Plating method, semiconductor device fabrication method and circuit board fabrication method Mar 8, 2011 Issued
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