
Jenny L. Wagner
Supervisory Patent Examiner (ID: 9120, Phone: (571)272-5359 , Office: P/2848 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, 2848, 2800, 2112 |
| Total Applications | 432 |
| Issued Applications | 298 |
| Pending Applications | 0 |
| Abandoned Applications | 134 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9286132
[patent_doc_number] => 08642461
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Side wettable plating for semiconductor chip package'
[patent_app_type] => utility
[patent_app_number] => 13/189857
[patent_app_country] => US
[patent_app_date] => 2011-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 7024
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13189857
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/189857 | Side wettable plating for semiconductor chip package | Jul 24, 2011 | Issued |
Array
(
[id] => 9127796
[patent_doc_number] => 08575747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-05
[patent_title] => 'Clip interconnect with encapsulation material locking feature'
[patent_app_type] => utility
[patent_app_number] => 13/189074
[patent_app_country] => US
[patent_app_date] => 2011-07-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/189074 | Clip interconnect with encapsulation material locking feature | Jul 21, 2011 | Issued |
Array
(
[id] => 8615390
[patent_doc_number] => 20130020702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-24
[patent_title] => 'DOUBLE-SIDED FLIP CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/188287
[patent_app_country] => US
[patent_app_date] => 2011-07-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/188287 | DOUBLE-SIDED FLIP CHIP PACKAGE | Jul 20, 2011 | Abandoned |
Array
(
[id] => 8926637
[patent_doc_number] => 20130182397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'Circuit Board Structure Used for Vehicle-Mounted Electronic Device'
[patent_app_type] => utility
[patent_app_number] => 13/812141
[patent_app_country] => US
[patent_app_date] => 2011-07-20
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/812141 | Circuit Board Structure Used for Vehicle-Mounted Electronic Device | Jul 19, 2011 | Abandoned |
Array
(
[id] => 8582147
[patent_doc_number] => 20130000968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => '1-Layer Interposer Substrate With Through-Substrate Posts'
[patent_app_type] => utility
[patent_app_number] => 13/173689
[patent_app_country] => US
[patent_app_date] => 2011-06-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/173689 | 1-Layer Interposer Substrate With Through-Substrate Posts | Jun 29, 2011 | Abandoned |
Array
(
[id] => 7801531
[patent_doc_number] => 08129804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Electronic device, resonator, oscillator and method for manufacturing electronic device'
[patent_app_type] => utility
[patent_app_number] => 13/168561
[patent_app_country] => US
[patent_app_date] => 2011-06-24
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[pdf_file] => patents/08/129/08129804.pdf
[firstpage_image] =>[orig_patent_app_number] => 13168561
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/168561 | Electronic device, resonator, oscillator and method for manufacturing electronic device | Jun 23, 2011 | Issued |
Array
(
[id] => 8918833
[patent_doc_number] => RE044376
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2013-07-16
[patent_title] => 'Silicon substrate with reduced surface roughness'
[patent_app_type] => reissue
[patent_app_number] => 13/117881
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/117881 | Silicon substrate with reduced surface roughness | May 26, 2011 | Issued |
Array
(
[id] => 9216256
[patent_doc_number] => 08629056
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-14
[patent_title] => 'Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections'
[patent_app_type] => utility
[patent_app_number] => 13/107549
[patent_app_country] => US
[patent_app_date] => 2011-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/107549 | Method for forming self-assembled mono-layer liner for cu/porous low-k interconnections | May 12, 2011 | Issued |
Array
(
[id] => 8706628
[patent_doc_number] => 20130063917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-14
[patent_title] => 'PRINTED CIRCUIT BOARD INCLUDING UNDER-FILL DAM AND FABRICATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/699275
[patent_app_country] => US
[patent_app_date] => 2011-05-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/699275 | Printed circuit board including under-fill dam and fabrication method thereof | May 10, 2011 | Issued |
Array
(
[id] => 8766130
[patent_doc_number] => 20130094166
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[patent_issue_date] => 2013-04-18
[patent_title] => 'DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 13/701541
[patent_app_country] => US
[patent_app_date] => 2011-05-11
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13701541
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/701541 | DISPLAY APPARATUS | May 10, 2011 | Abandoned |
Array
(
[id] => 5932587
[patent_doc_number] => 20110210451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-01
[patent_title] => 'METHODS OF FORMING A METAL PATTERN AND SEMICONDUCTOR DEVICE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/104215
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[pdf_file] => publications/A1/0210/20110210451.pdf
[firstpage_image] =>[orig_patent_app_number] => 13104215
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/104215 | Methods of forming a metal pattern and semiconductor device structure | May 9, 2011 | Issued |
Array
(
[id] => 6042409
[patent_doc_number] => 20110204486
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[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/098648 | Method of manufacturing a semiconductor integrated circuit device | May 1, 2011 | Issued |
Array
(
[id] => 8317874
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[patent_title] => 'Semiconductor package through-electrode suitable for a stacked semiconductor package and semiconductor package having the same'
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[patent_app_number] => 13/089666
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Array
(
[id] => 6106185
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[patent_title] => 'EDGE CONNECT WAFER LEVEL STACKING'
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Array
(
[id] => 6106173
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/085759 | Solder bump interconnect | Apr 12, 2011 | Issued |
Array
(
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Array
(
[id] => 6106105
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/043854 | Plating method, semiconductor device fabrication method and circuit board fabrication method | Mar 8, 2011 | Issued |