Search

Jenny L. Wagner

Supervisory Patent Examiner (ID: 9120, Phone: (571)272-5359 , Office: P/2848 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2848, 2800, 2112
Total Applications
432
Issued Applications
298
Pending Applications
0
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7573613 [patent_doc_number] => 20110269269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS' [patent_app_type] => utility [patent_app_number] => 12/772896 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5989 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20110269269.pdf [firstpage_image] =>[orig_patent_app_number] => 12772896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772896
LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS May 2, 2010 Abandoned
Array ( [id] => 8363600 [patent_doc_number] => 08252665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Protection layer for adhesive material at wafer edge' [patent_app_type] => utility [patent_app_number] => 12/769725 [patent_app_country] => US [patent_app_date] => 2010-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12769725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769725
Protection layer for adhesive material at wafer edge Apr 28, 2010 Issued
Array ( [id] => 7570605 [patent_doc_number] => 20110266260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Welding Electrode With Contoured Face' [patent_app_type] => utility [patent_app_number] => 12/768928 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3273 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266260.pdf [firstpage_image] =>[orig_patent_app_number] => 12768928 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768928
Welding electrode with contoured face Apr 27, 2010 Issued
Array ( [id] => 8664355 [patent_doc_number] => 08377816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of forming electrical connections' [patent_app_type] => utility [patent_app_number] => 12/768025 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12768025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768025
Method of forming electrical connections Apr 26, 2010 Issued
Array ( [id] => 6529111 [patent_doc_number] => 20100203722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Semiconductor Device Having a Second Level of Metallization Formed over a First Level with Minimal Damage to the First Level and Method' [patent_app_type] => utility [patent_app_number] => 12/765662 [patent_app_country] => US [patent_app_date] => 2010-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20100203722.pdf [firstpage_image] =>[orig_patent_app_number] => 12765662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/765662
Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method Apr 21, 2010 Issued
Array ( [id] => 6529140 [patent_doc_number] => 20100203724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/764411 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 17267 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20100203724.pdf [firstpage_image] =>[orig_patent_app_number] => 12764411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764411
Method of manufacturing a semiconductor integrated circuit device Apr 20, 2010 Issued
Array ( [id] => 6570225 [patent_doc_number] => 20100273323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'PRE-TREATMENT METHOD TO INCREASE COPPER ISLAND DENSITY OF CU ON BARRIER LAYERS' [patent_app_type] => utility [patent_app_number] => 12/764721 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6172 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273323.pdf [firstpage_image] =>[orig_patent_app_number] => 12764721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764721
Pre-treatment method to increase copper island density of CU on barrier layers Apr 20, 2010 Issued
Array ( [id] => 6528575 [patent_doc_number] => 20100203685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP' [patent_app_type] => utility [patent_app_number] => 12/762404 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2464 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20100203685.pdf [firstpage_image] =>[orig_patent_app_number] => 12762404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762404
Semiconductor chips with reduced stress from underfill at edge of chip Apr 18, 2010 Issued
Array ( [id] => 6570262 [patent_doc_number] => 20100273325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/762821 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273325.pdf [firstpage_image] =>[orig_patent_app_number] => 12762821 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762821
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Apr 18, 2010 Abandoned
Array ( [id] => 7511005 [patent_doc_number] => 20110256715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'BARRIER LAYER FOR COPPER INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 12/761805 [patent_app_country] => US [patent_app_date] => 2010-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4405 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256715.pdf [firstpage_image] =>[orig_patent_app_number] => 12761805 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/761805
Barrier layer for copper interconnect Apr 15, 2010 Issued
Array ( [id] => 8625375 [patent_doc_number] => 08357870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-22 [patent_title] => 'Intelligent stepper welding system and method' [patent_app_type] => utility [patent_app_number] => 12/728821 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12728821 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728821
Intelligent stepper welding system and method Mar 21, 2010 Issued
Array ( [id] => 8422110 [patent_doc_number] => 08278598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Methods and systems for resistance spot welding using direct current micro pulses' [patent_app_type] => utility [patent_app_number] => 12/726450 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4278 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12726450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726450
Methods and systems for resistance spot welding using direct current micro pulses Mar 17, 2010 Issued
Array ( [id] => 6614667 [patent_doc_number] => 20100224978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEX TAPE AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/717085 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20100224978.pdf [firstpage_image] =>[orig_patent_app_number] => 12717085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717085
Integrated circuit packaging system with flex tape and method of manufacture thereof Mar 2, 2010 Issued
Array ( [id] => 6280603 [patent_doc_number] => 20100155929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Chip-Stacked Package Structure' [patent_app_type] => utility [patent_app_number] => 12/713333 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8320 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155929.pdf [firstpage_image] =>[orig_patent_app_number] => 12713333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713333
Chip-Stacked Package Structure Feb 25, 2010 Abandoned
Array ( [id] => 8981948 [patent_doc_number] => 08513062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method of manufacturing a semiconductor device with a carrier having a cavity and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/706555 [patent_app_country] => US [patent_app_date] => 2010-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 7224 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12706555 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/706555
Method of manufacturing a semiconductor device with a carrier having a cavity and semiconductor device Feb 15, 2010 Issued
Array ( [id] => 8555787 [patent_doc_number] => 08330262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Processes for enhanced 3D integration and structures generated using the same' [patent_app_type] => utility [patent_app_number] => 12/698529 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8295 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698529
Processes for enhanced 3D integration and structures generated using the same Feb 1, 2010 Issued
Array ( [id] => 6170038 [patent_doc_number] => 20110175219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'METHOD FOR MODULAR ARRANGEMENT OF A SILICON BASED ARRAY AND MODULAR SILICON BASED ARRAY' [patent_app_type] => utility [patent_app_number] => 12/689910 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6094 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175219.pdf [firstpage_image] =>[orig_patent_app_number] => 12689910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689910
Method for modular arrangement of a silicon based array and modular silicon based array Jan 18, 2010 Issued
Array ( [id] => 6317936 [patent_doc_number] => 20100112775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'PLATING METHOD, SEMICONDUCTOR DEVICE FABRICATION METHOD AND CIRCUIT BOARD FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/684570 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 24229 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20100112775.pdf [firstpage_image] =>[orig_patent_app_number] => 12684570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684570
Plating method, semiconductor device fabrication method and circuit board fabrication method Jan 7, 2010 Issued
Array ( [id] => 4431941 [patent_doc_number] => 07968445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Semiconductor package with passivation island for reducing stress on solder bumps' [patent_app_type] => utility [patent_app_number] => 12/651758 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4534 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968445.pdf [firstpage_image] =>[orig_patent_app_number] => 12651758 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651758
Semiconductor package with passivation island for reducing stress on solder bumps Jan 3, 2010 Issued
Array ( [id] => 4489250 [patent_doc_number] => 07884486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Chip-stacked package structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/648655 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6678 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884486.pdf [firstpage_image] =>[orig_patent_app_number] => 12648655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648655
Chip-stacked package structure and method for manufacturing the same Dec 28, 2009 Issued
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