Search

Jenny L. Wagner

Supervisory Patent Examiner (ID: 9120, Phone: (571)272-5359 , Office: P/2848 )

Most Active Art Unit
2891
Art Unit(s)
2891, 2848, 2800, 2112
Total Applications
432
Issued Applications
298
Pending Applications
0
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6418975 [patent_doc_number] => 20100167468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/648276 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2707 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167468.pdf [firstpage_image] =>[orig_patent_app_number] => 12648276 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648276
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Dec 27, 2009 Abandoned
Array ( [id] => 8543305 [patent_doc_number] => 08318595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Self-assembled electrical contacts' [patent_app_type] => utility [patent_app_number] => 12/625189 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4708 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12625189 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625189
Self-assembled electrical contacts Nov 23, 2009 Issued
Array ( [id] => 5980316 [patent_doc_number] => 20110095423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND ITS MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/000391 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6543 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20110095423.pdf [firstpage_image] =>[orig_patent_app_number] => 13000391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/000391
Semiconductor device mounted structure and its manufacturing method Oct 26, 2009 Issued
Array ( [id] => 8270854 [patent_doc_number] => 08212362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/603106 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 69 [patent_no_of_words] => 28124 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12603106 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603106
Semiconductor device Oct 20, 2009 Issued
Array ( [id] => 8200735 [patent_doc_number] => 08187964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Integrated circuit device and method' [patent_app_type] => utility [patent_app_number] => 12/581573 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1524 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/187/08187964.pdf [firstpage_image] =>[orig_patent_app_number] => 12581573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581573
Integrated circuit device and method Oct 18, 2009 Issued
Array ( [id] => 6601019 [patent_doc_number] => 20100032840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Semiconductor Device with an Improved Solder Joint' [patent_app_type] => utility [patent_app_number] => 12/581254 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4815 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20100032840.pdf [firstpage_image] =>[orig_patent_app_number] => 12581254 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581254
Semiconductor device with an improved solder joint Oct 18, 2009 Issued
Array ( [id] => 6349983 [patent_doc_number] => 20100021656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION' [patent_app_type] => utility [patent_app_number] => 12/573407 [patent_app_country] => US [patent_app_date] => 2009-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4501 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20100021656.pdf [firstpage_image] =>[orig_patent_app_number] => 12573407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/573407
Low leakage metal-containing cap process using oxidation Oct 4, 2009 Issued
Array ( [id] => 6348233 [patent_doc_number] => 20100330741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'FABRICATION METHOD FOR SYSTEM-ON-CHIP (SOC) MODULE' [patent_app_type] => utility [patent_app_number] => 12/570049 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2842 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330741.pdf [firstpage_image] =>[orig_patent_app_number] => 12570049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570049
FABRICATION METHOD FOR SYSTEM-ON-CHIP (SOC) MODULE Sep 29, 2009 Abandoned
Array ( [id] => 6114674 [patent_doc_number] => 20110074044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/569200 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 20753 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074044.pdf [firstpage_image] =>[orig_patent_app_number] => 12569200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569200
Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication Sep 28, 2009 Issued
Array ( [id] => 6358531 [patent_doc_number] => 20100078746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/568820 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20100078746.pdf [firstpage_image] =>[orig_patent_app_number] => 12568820 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568820
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Sep 28, 2009 Abandoned
Array ( [id] => 7527899 [patent_doc_number] => 08044494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Stackable molded packages and methods of making the same' [patent_app_type] => utility [patent_app_number] => 12/567469 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3650 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/044/08044494.pdf [firstpage_image] =>[orig_patent_app_number] => 12567469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567469
Stackable molded packages and methods of making the same Sep 24, 2009 Issued
Array ( [id] => 5972695 [patent_doc_number] => 20110068448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAP LAYER AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/564852 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20110068448.pdf [firstpage_image] =>[orig_patent_app_number] => 12564852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564852
Integrated circuit packaging system with cap layer and method of manufacture thereof Sep 21, 2009 Issued
Array ( [id] => 5972733 [patent_doc_number] => 20110068479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'ASSEMBLY OF MULTI-CHIP MODULES USING SACRIFICIAL FEATURES' [patent_app_type] => utility [patent_app_number] => 12/564822 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20110068479.pdf [firstpage_image] =>[orig_patent_app_number] => 12564822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564822
Assembly of multi-chip modules using sacrificial features Sep 21, 2009 Issued
Array ( [id] => 7800984 [patent_doc_number] => 08129254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/563934 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5155 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129254.pdf [firstpage_image] =>[orig_patent_app_number] => 12563934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563934
Semiconductor device and manufacturing method thereof Sep 20, 2009 Issued
Array ( [id] => 8808362 [patent_doc_number] => 08446017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Stackable wafer level package and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 12/562387 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6050 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12562387 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562387
Stackable wafer level package and fabricating method thereof Sep 17, 2009 Issued
Array ( [id] => 6352888 [patent_doc_number] => 20100072629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Wiring Structure, Semiconductor Device Having the Wiring Structure, and Method for Manufacturing the Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/562019 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3680 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20100072629.pdf [firstpage_image] =>[orig_patent_app_number] => 12562019 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/562019
Wiring Structure, Semiconductor Device Having the Wiring Structure, and Method for Manufacturing the Semiconductor Device Sep 16, 2009 Abandoned
Array ( [id] => 6575902 [patent_doc_number] => 20100096752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/560579 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20100096752.pdf [firstpage_image] =>[orig_patent_app_number] => 12560579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560579
SEMICONDUCTOR DEVICE Sep 15, 2009 Abandoned
Array ( [id] => 6230451 [patent_doc_number] => 20100184255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'MANUFACTURING METHOD FOR PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/550959 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20100184255.pdf [firstpage_image] =>[orig_patent_app_number] => 12550959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550959
MANUFACTURING METHOD FOR PACKAGE STRUCTURE Aug 30, 2009 Abandoned
Array ( [id] => 6067866 [patent_doc_number] => 20110042803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Method For Fabricating A Through Interconnect On A Semiconductor Substrate' [patent_app_type] => utility [patent_app_number] => 12/545949 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4215 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20110042803.pdf [firstpage_image] =>[orig_patent_app_number] => 12545949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/545949
Method For Fabricating A Through Interconnect On A Semiconductor Substrate Aug 23, 2009 Abandoned
Array ( [id] => 4528801 [patent_doc_number] => 07923347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Controlling warping in integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 12/546083 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/923/07923347.pdf [firstpage_image] =>[orig_patent_app_number] => 12546083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546083
Controlling warping in integrated circuit devices Aug 23, 2009 Issued
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