Search

Jeremy C. Norris

Examiner (ID: 14672, Phone: (571)272-1932 , Office: P/2847 )

Most Active Art Unit
2847
Art Unit(s)
2841, 2831, 2835, 2847, 2827
Total Applications
2108
Issued Applications
1794
Pending Applications
93
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18458686 [patent_doc_number] => 20230199968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD FOR FORMING PATTERN ON SUBSTRATE STRUCTURE WITHOUT USING MASK LAYER AND SUBSTRATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/552982 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/552982
METHOD FOR FORMING PATTERN ON SUBSTRATE STRUCTURE WITHOUT USING MASK LAYER AND SUBSTRATE STRUCTURE Dec 15, 2021 Abandoned
Array ( [id] => 19079795 [patent_doc_number] => 11949178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Function module for electrical applications [patent_app_type] => utility [patent_app_number] => 17/551290 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551290
Function module for electrical applications Dec 14, 2021 Issued
Array ( [id] => 19973819 [patent_doc_number] => 12342451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Electronic component module and power supply device comprising same [patent_app_type] => utility [patent_app_number] => 18/265786 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18265786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/265786
Electronic component module and power supply device comprising same Dec 13, 2021 Issued
Array ( [id] => 17740033 [patent_doc_number] => 20220225495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => CONTROL CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 17/547039 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547039
CONTROL CIRCUIT BOARD Dec 8, 2021 Abandoned
Array ( [id] => 18442147 [patent_doc_number] => 20230189443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => Printed Circuit Board Layout [patent_app_type] => utility [patent_app_number] => 17/546812 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546812
Printed circuit board layout Dec 8, 2021 Issued
Array ( [id] => 19040313 [patent_doc_number] => 20240090128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => WIRING CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 18/261231 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/261231
WIRING CIRCUIT BOARD Dec 2, 2021 Issued
Array ( [id] => 17479506 [patent_doc_number] => 20220087010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => FLEXIBLE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/457059 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457059
Flexible substrate Nov 30, 2021 Issued
Array ( [id] => 18706387 [patent_doc_number] => 11792918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Co-axial via structure [patent_app_type] => utility [patent_app_number] => 17/455918 [patent_app_country] => US [patent_app_date] => 2021-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 4498 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455918 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455918
Co-axial via structure Nov 20, 2021 Issued
Array ( [id] => 18189696 [patent_doc_number] => 11580287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Isolation of compartments in a layered printed circuit board, and apparatus and methods for the same [patent_app_type] => utility [patent_app_number] => 17/530874 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530874
Isolation of compartments in a layered printed circuit board, and apparatus and methods for the same Nov 18, 2021 Issued
Array ( [id] => 18107071 [patent_doc_number] => 11546984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Architecture for chip-to-chip interconnection in semiconductors [patent_app_type] => utility [patent_app_number] => 17/530449 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 7742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530449
Architecture for chip-to-chip interconnection in semiconductors Nov 17, 2021 Issued
Array ( [id] => 19287930 [patent_doc_number] => 20240224413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/555866 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18555866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/555866
WIRING SUBSTRATE Nov 15, 2021 Pending
Array ( [id] => 19139412 [patent_doc_number] => 11974404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Method of producing circuit boards [patent_app_type] => utility [patent_app_number] => 17/527352 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 7762 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527352
Method of producing circuit boards Nov 15, 2021 Issued
Array ( [id] => 18516218 [patent_doc_number] => 20230232540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 17/998966 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998966
Method of manufacturing printed circuit board Nov 15, 2021 Issued
Array ( [id] => 18281424 [patent_doc_number] => 20230096896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => TENSILE ELECTRONIC MODULE AND ELECTRONIC DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/453541 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453541
Tensile electronic module and electronic device using the same Nov 3, 2021 Issued
Array ( [id] => 18992971 [patent_doc_number] => 20240064940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => ELECTRONIC ASSEMBLY [patent_app_type] => utility [patent_app_number] => 18/267988 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18267988 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/267988
ELECTRONIC ASSEMBLY Nov 2, 2021 Pending
Array ( [id] => 17585092 [patent_doc_number] => 20220141947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => ARRANGEMENT FOR HEAT EXCHANGE [patent_app_type] => utility [patent_app_number] => 17/516457 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516457
Arrangement for heat exchange Oct 31, 2021 Issued
Array ( [id] => 18344218 [patent_doc_number] => 11641710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-02 [patent_title] => Circuit board ground via patterns for minimizing crosstalk between signal vias [patent_app_type] => utility [patent_app_number] => 17/516038 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3758 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516038
Circuit board ground via patterns for minimizing crosstalk between signal vias Oct 31, 2021 Issued
Array ( [id] => 18352703 [patent_doc_number] => 20230140814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MICROELECTRONIC TEST INTERFACE SUBSTRATES, DEVICES, AND METHODS OF MANUFACTURE THEREOF PROBE HEAD TEST CONTACT PIN SHIELD AND DIELECTRIC INSULATION ON TOP LAYER OF BUILDUP REDISTRIBUTION LAYER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/515404 [patent_app_country] => US [patent_app_date] => 2021-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515404
MICROELECTRONIC TEST INTERFACE SUBSTRATES, DEVICES, AND METHODS OF MANUFACTURE THEREOF PROBE HEAD TEST CONTACT PIN SHIELD AND DIELECTRIC INSULATION ON TOP LAYER OF BUILDUP REDISTRIBUTION LAYER SYSTEM Oct 29, 2021 Abandoned
Array ( [id] => 20637809 [patent_doc_number] => 12598703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Wiring circuit board [patent_app_type] => utility [patent_app_number] => 18/253892 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 2536 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18253892 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/253892
WIRING CIRCUIT BOARD Oct 28, 2021 Issued
Array ( [id] => 19193450 [patent_doc_number] => 20240172363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DISPLAY MODULE AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/912627 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17912627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/912627
Display module and display apparatus Oct 24, 2021 Issued
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