Search

Jeremy C. Norris

Examiner (ID: 7122, Phone: (571)272-1932 , Office: P/2847 )

Most Active Art Unit
2847
Art Unit(s)
2847, 2841, 2835, 2827, 2831
Total Applications
2133
Issued Applications
1816
Pending Applications
90
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6450809 [patent_doc_number] => 20100089624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'MULTILAYER CERAMIC SUBSTRATE AND PROCESS FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/523813 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4238 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20100089624.pdf [firstpage_image] =>[orig_patent_app_number] => 12523813 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/523813
MULTILAYER CERAMIC SUBSTRATE AND PROCESS FOR PRODUCING THE SAME Feb 11, 2008 Abandoned
Array ( [id] => 6436507 [patent_doc_number] => 20100282497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/812600 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2707 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20100282497.pdf [firstpage_image] =>[orig_patent_app_number] => 12812600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/812600
CIRCUIT BOARD Feb 6, 2008 Abandoned
Array ( [id] => 4952154 [patent_doc_number] => 20080185178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Circuit board and method for manufacturing the same, semiconductor package, component built-in module and board for electronic equipment' [patent_app_type] => utility [patent_app_number] => 12/011725 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8650 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20080185178.pdf [firstpage_image] =>[orig_patent_app_number] => 12011725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/011725
Circuit board and method for manufacturing the same, semiconductor package, component built-in module and board for electronic equipment Jan 28, 2008 Abandoned
Array ( [id] => 6419015 [patent_doc_number] => 20100101843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'INSULATING RESIN SHEET LAMINATE AND MULTI-LAYER PRINTED CIRCUIT BOARD INCLUDING INSULATING RESIN SHEET LAMINATE' [patent_app_type] => utility [patent_app_number] => 12/523127 [patent_app_country] => US [patent_app_date] => 2008-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12007 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20100101843.pdf [firstpage_image] =>[orig_patent_app_number] => 12523127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/523127
Insulating resin sheet laminate and multi-layer printed circuit board including insulating resin sheet laminate Jan 15, 2008 Issued
Array ( [id] => 22153 [patent_doc_number] => 07799615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Power converter package and thermal management' [patent_app_type] => utility [patent_app_number] => 12/014662 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 35 [patent_no_of_words] => 9456 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799615.pdf [firstpage_image] =>[orig_patent_app_number] => 12014662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014662
Power converter package and thermal management Jan 14, 2008 Issued
Array ( [id] => 4912518 [patent_doc_number] => 20080093117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'MULTILAYER CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/968700 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7654 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20080093117.pdf [firstpage_image] =>[orig_patent_app_number] => 11968700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968700
Multilayer circuit board and manufacturing method thereof Jan 2, 2008 Issued
Array ( [id] => 123766 [patent_doc_number] => 07705246 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'Compact differential signal via structure' [patent_app_type] => utility [patent_app_number] => 11/965811 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 1826 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705246.pdf [firstpage_image] =>[orig_patent_app_number] => 11965811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965811
Compact differential signal via structure Dec 27, 2007 Issued
Array ( [id] => 4963152 [patent_doc_number] => 20080105972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Method for making a circuit plate' [patent_app_type] => utility [patent_app_number] => 12/004610 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2658 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105972.pdf [firstpage_image] =>[orig_patent_app_number] => 12004610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004610
Method for making a circuit plate Dec 20, 2007 Abandoned
Array ( [id] => 5293219 [patent_doc_number] => 20090008145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'EMBEDDED CIRCUIT STRUCTURE AND FABRICATING PROCESS OF THE SAME' [patent_app_type] => utility [patent_app_number] => 11/958920 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4125 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008145.pdf [firstpage_image] =>[orig_patent_app_number] => 11958920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958920
Embedded circuit structure and fabricating process of the same Dec 17, 2007 Issued
Array ( [id] => 4762260 [patent_doc_number] => 20080173469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Multilayer wiring board' [patent_app_type] => utility [patent_app_number] => 12/000730 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8514 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173469.pdf [firstpage_image] =>[orig_patent_app_number] => 12000730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000730
Multilayer wiring board Dec 16, 2007 Issued
Array ( [id] => 4742856 [patent_doc_number] => 20080087457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring' [patent_app_type] => utility [patent_app_number] => 11/951646 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6280 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20080087457.pdf [firstpage_image] =>[orig_patent_app_number] => 11951646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951646
Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring Dec 5, 2007 Abandoned
Array ( [id] => 4866989 [patent_doc_number] => 20080146048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'PRINTED CIRCUIT BOARD CONNECTION' [patent_app_type] => utility [patent_app_number] => 11/950825 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2151 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20080146048.pdf [firstpage_image] =>[orig_patent_app_number] => 11950825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950825
PRINTED CIRCUIT BOARD CONNECTION Dec 4, 2007 Abandoned
Array ( [id] => 4788890 [patent_doc_number] => 20080289863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'SURFACE FINISH STRUCTURE OF MULTI-LAYER SUBSTRATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/950816 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3166 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20080289863.pdf [firstpage_image] =>[orig_patent_app_number] => 11950816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950816
Surface finish structure of multi-layer substrate and manufacturing method thereof Dec 4, 2007 Issued
Array ( [id] => 8283171 [patent_doc_number] => 08217275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Sealing material and mounting method using the sealing material' [patent_app_type] => utility [patent_app_number] => 12/517311 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8880 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12517311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/517311
Sealing material and mounting method using the sealing material Dec 2, 2007 Issued
Array ( [id] => 4918636 [patent_doc_number] => 20080066945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'METHOD FOR MAKING CABLE WITH A CONDUCTIVE BUMP ARRAY, AND METHOD FOR CONNECTING THE CABLE TO A TASK OBJECT' [patent_app_type] => utility [patent_app_number] => 11/945511 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20080066945.pdf [firstpage_image] =>[orig_patent_app_number] => 11945511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945511
Method for making cable with a conductive bump array, and method for connecting the cable to a task object Nov 26, 2007 Issued
Array ( [id] => 5446281 [patent_doc_number] => 20090047507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Multilayer printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/986432 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6644 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20090047507.pdf [firstpage_image] =>[orig_patent_app_number] => 11986432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986432
Multilayer printed circuit board Nov 20, 2007 Issued
Array ( [id] => 4805547 [patent_doc_number] => 20080169125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Novel interconnection structure for improving signal integrity' [patent_app_type] => utility [patent_app_number] => 11/986323 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11430 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20080169125.pdf [firstpage_image] =>[orig_patent_app_number] => 11986323 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986323
Interconnection structure for improving signal integrity Nov 19, 2007 Issued
Array ( [id] => 5406012 [patent_doc_number] => 20090119910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'COMPONENT WITH BONDING ADHESIVE' [patent_app_type] => utility [patent_app_number] => 11/939804 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3416 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119910.pdf [firstpage_image] =>[orig_patent_app_number] => 11939804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939804
Component with bonding adhesive Nov 13, 2007 Issued
Array ( [id] => 112857 [patent_doc_number] => 07719124 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Printed wiring board for mounting components' [patent_app_type] => utility [patent_app_number] => 11/938635 [patent_app_country] => US [patent_app_date] => 2007-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4444 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719124.pdf [firstpage_image] =>[orig_patent_app_number] => 11938635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/938635
Printed wiring board for mounting components Nov 11, 2007 Issued
Array ( [id] => 4883261 [patent_doc_number] => 20080257593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Printed circuit board, method of manufacturing the same, and apparatus for perforating via holes' [patent_app_type] => utility [patent_app_number] => 11/979833 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20080257593.pdf [firstpage_image] =>[orig_patent_app_number] => 11979833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979833
Printed circuit board, method of manufacturing the same, and apparatus for perforating via holes Nov 7, 2007 Issued
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