
Jeremy C. Norris
Examiner (ID: 7122, Phone: (571)272-1932 , Office: P/2847 )
| Most Active Art Unit | 2847 |
| Art Unit(s) | 2847, 2841, 2835, 2827, 2831 |
| Total Applications | 2133 |
| Issued Applications | 1816 |
| Pending Applications | 90 |
| Abandoned Applications | 249 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5188747
[patent_doc_number] => 20070167056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-19
[patent_title] => 'Multi-layer printed circuit board, and method for detecting errors in laminating order of layers thereof'
[patent_app_type] => utility
[patent_app_number] => 11/332301
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3296
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20070167056.pdf
[firstpage_image] =>[orig_patent_app_number] => 11332301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/332301 | Multi-layer printed circuit board, and method for detecting errors in laminating order of layers thereof | Jan 16, 2006 | Abandoned |
Array
(
[id] => 122453
[patent_doc_number] => 07709746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Pb-free solder-connected structure and electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/331220
[patent_app_country] => US
[patent_app_date] => 2006-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 5277
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/709/07709746.pdf
[firstpage_image] =>[orig_patent_app_number] => 11331220
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/331220 | Pb-free solder-connected structure and electronic device | Jan 12, 2006 | Issued |
Array
(
[id] => 5628890
[patent_doc_number] => 20060145358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Printed circuit board having reduced mounting height'
[patent_app_type] => utility
[patent_app_number] => 11/320861
[patent_app_country] => US
[patent_app_date] => 2005-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2024
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145358.pdf
[firstpage_image] =>[orig_patent_app_number] => 11320861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/320861 | Printed circuit board having reduced mounting height | Dec 29, 2005 | Issued |
Array
(
[id] => 5771835
[patent_doc_number] => 20060101639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Method of making innerlayer panels and printed wiring boards using X-ray identification of fiducials'
[patent_app_type] => utility
[patent_app_number] => 11/321934
[patent_app_country] => US
[patent_app_date] => 2005-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5160
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20060101639.pdf
[firstpage_image] =>[orig_patent_app_number] => 11321934
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/321934 | Innerlayer panels and printed wiring boards with embedded fiducials | Dec 28, 2005 | Issued |
Array
(
[id] => 5018804
[patent_doc_number] => 20070144769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Method and apparatus for a printed circuit board using laser assisted metallization and patterning of a substrate'
[patent_app_type] => utility
[patent_app_number] => 11/320922
[patent_app_country] => US
[patent_app_date] => 2005-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7235
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20070144769.pdf
[firstpage_image] =>[orig_patent_app_number] => 11320922
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/320922 | Method and apparatus for a printed circuit board using laser assisted metallization and patterning of a substrate | Dec 27, 2005 | Issued |
Array
(
[id] => 5683173
[patent_doc_number] => 20060199443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Printed circuit board and display device using the same'
[patent_app_type] => utility
[patent_app_number] => 11/317316
[patent_app_country] => US
[patent_app_date] => 2005-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 909
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20060199443.pdf
[firstpage_image] =>[orig_patent_app_number] => 11317316
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/317316 | Printed circuit board and display device using the same | Dec 22, 2005 | Abandoned |
Array
(
[id] => 5628148
[patent_doc_number] => 20060144616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Printed circuit board with improved ground plane'
[patent_app_type] => utility
[patent_app_number] => 11/316300
[patent_app_country] => US
[patent_app_date] => 2005-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 1872
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20060144616.pdf
[firstpage_image] =>[orig_patent_app_number] => 11316300
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/316300 | Printed circuit board with improved ground plane | Dec 20, 2005 | Abandoned |
Array
(
[id] => 103430
[patent_doc_number] => 07723616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-25
[patent_title] => 'Superconducting cable and DC transmission system incorporating the superconducting cable'
[patent_app_type] => utility
[patent_app_number] => 11/795515
[patent_app_country] => US
[patent_app_date] => 2005-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 15408
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/723/07723616.pdf
[firstpage_image] =>[orig_patent_app_number] => 11795515
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/795515 | Superconducting cable and DC transmission system incorporating the superconducting cable | Dec 15, 2005 | Issued |
Array
(
[id] => 6495554
[patent_doc_number] => 20100012367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-21
[patent_title] => 'PRINTED CIRCUIT BOARD ARRANGEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/722342
[patent_app_country] => US
[patent_app_date] => 2005-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1627
[patent_no_of_claims] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20100012367.pdf
[firstpage_image] =>[orig_patent_app_number] => 11722342
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/722342 | PRINTED CIRCUIT BOARD ARRANGEMENT | Dec 13, 2005 | Abandoned |
Array
(
[id] => 185780
[patent_doc_number] => 07645942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Electrical interconnect with maximized electrical contact'
[patent_app_type] => utility
[patent_app_number] => 11/298421
[patent_app_country] => US
[patent_app_date] => 2005-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1629
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/645/07645942.pdf
[firstpage_image] =>[orig_patent_app_number] => 11298421
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/298421 | Electrical interconnect with maximized electrical contact | Dec 8, 2005 | Issued |
Array
(
[id] => 318927
[patent_doc_number] => 07521637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-21
[patent_title] => 'Multilayer printed circuit board having via arrangements for reducing crosstalk among vias'
[patent_app_type] => utility
[patent_app_number] => 11/297303
[patent_app_country] => US
[patent_app_date] => 2005-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1611
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/521/07521637.pdf
[firstpage_image] =>[orig_patent_app_number] => 11297303
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/297303 | Multilayer printed circuit board having via arrangements for reducing crosstalk among vias | Dec 7, 2005 | Issued |
Array
(
[id] => 5233417
[patent_doc_number] => 20070125572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Thin circuit board'
[patent_app_type] => utility
[patent_app_number] => 11/295203
[patent_app_country] => US
[patent_app_date] => 2005-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2121
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20070125572.pdf
[firstpage_image] =>[orig_patent_app_number] => 11295203
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/295203 | Thin circuit board | Dec 4, 2005 | Issued |
Array
(
[id] => 5233416
[patent_doc_number] => 20070125571
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Column grid array using compliant core'
[patent_app_type] => utility
[patent_app_number] => 11/292694
[patent_app_country] => US
[patent_app_date] => 2005-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 4062
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[pdf_file] => publications/A1/0125/20070125571.pdf
[firstpage_image] =>[orig_patent_app_number] => 11292694
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/292694 | Column grid array using compliant core | Dec 1, 2005 | Issued |
Array
(
[id] => 191155
[patent_doc_number] => 07642467
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-01-05
[patent_title] => 'Method for fabrication of separators for electrode pairs in diodes'
[patent_app_type] => utility
[patent_app_number] => 11/293411
[patent_app_country] => US
[patent_app_date] => 2005-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/642/07642467.pdf
[firstpage_image] =>[orig_patent_app_number] => 11293411
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/293411 | Method for fabrication of separators for electrode pairs in diodes | Dec 1, 2005 | Issued |
Array
(
[id] => 5840344
[patent_doc_number] => 20060120056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Circuit component module, electronic circuit device, and method for manufacturing the circuit component module'
[patent_app_type] => utility
[patent_app_number] => 11/290314
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[pdf_file] => publications/A1/0120/20060120056.pdf
[firstpage_image] =>[orig_patent_app_number] => 11290314
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/290314 | Circuit component module, electronic circuit device, and method for manufacturing the circuit component module | Nov 28, 2005 | Issued |
Array
(
[id] => 122456
[patent_doc_number] => 07709747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Matched-impedance surface-mount technology footprints'
[patent_app_type] => utility
[patent_app_number] => 11/287926
[patent_app_country] => US
[patent_app_date] => 2005-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/709/07709747.pdf
[firstpage_image] =>[orig_patent_app_number] => 11287926
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/287926 | Matched-impedance surface-mount technology footprints | Nov 27, 2005 | Issued |
Array
(
[id] => 8017839
[patent_doc_number] => 08138423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Printed wiring board and method for manufacturing printed wiring board'
[patent_app_type] => utility
[patent_app_number] => 11/719803
[patent_app_country] => US
[patent_app_date] => 2005-11-18
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/138/08138423.pdf
[firstpage_image] =>[orig_patent_app_number] => 11719803
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/719803 | Printed wiring board and method for manufacturing printed wiring board | Nov 17, 2005 | Issued |
Array
(
[id] => 7978267
[patent_doc_number] => 08071881
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Wiring board, method for manufacturing same and semiconductor device'
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[pdf_file] => patents/08/071/08071881.pdf
[firstpage_image] =>[orig_patent_app_number] => 11719313
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/719313 | Wiring board, method for manufacturing same and semiconductor device | Nov 16, 2005 | Issued |
Array
(
[id] => 377304
[patent_doc_number] => 07312405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-25
[patent_title] => 'Module structure having embedded chips'
[patent_app_type] => utility
[patent_app_number] => 11/273752
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[pdf_file] => patents/07/312/07312405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11273752
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273752 | Module structure having embedded chips | Nov 13, 2005 | Issued |
Array
(
[id] => 356461
[patent_doc_number] => 07488898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-10
[patent_title] => 'Land structure, printed wiring board, and electronic device'
[patent_app_type] => utility
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/488/07488898.pdf
[firstpage_image] =>[orig_patent_app_number] => 11270102
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/270102 | Land structure, printed wiring board, and electronic device | Nov 8, 2005 | Issued |