Search

Jeremy C. Norris

Examiner (ID: 7122, Phone: (571)272-1932 , Office: P/2847 )

Most Active Art Unit
2847
Art Unit(s)
2847, 2841, 2835, 2827, 2831
Total Applications
2133
Issued Applications
1816
Pending Applications
90
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7119847 [patent_doc_number] => 20050011676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Alternating voided areas of anti-pads' [patent_app_type] => utility [patent_app_number] => 10/621925 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3901 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20050011676.pdf [firstpage_image] =>[orig_patent_app_number] => 10621925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621925
Alternating voided areas of anti-pads Jul 16, 2003 Issued
Array ( [id] => 7119846 [patent_doc_number] => 20050011675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Partially voided anit-pads' [patent_app_type] => utility [patent_app_number] => 10/621661 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2553 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20050011675.pdf [firstpage_image] =>[orig_patent_app_number] => 10621661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621661
Partially voided anti-pads Jul 16, 2003 Issued
Array ( [id] => 7346677 [patent_doc_number] => 20040011556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Printed circuit board and soldering structure for electronic parts thereto' [patent_app_type] => new [patent_app_number] => 10/618593 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2079 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20040011556.pdf [firstpage_image] =>[orig_patent_app_number] => 10618593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618593
Printed circuit board and structure for soldering electronic parts thereto Jul 14, 2003 Issued
Array ( [id] => 7355583 [patent_doc_number] => 20040003943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Multilayer circuit board and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/612990 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6805 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003943.pdf [firstpage_image] =>[orig_patent_app_number] => 10612990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612990
Multilayer circuit board and method of manufacturing the same Jul 6, 2003 Abandoned
Array ( [id] => 7202002 [patent_doc_number] => 20040069529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers' [patent_app_type] => new [patent_app_number] => 10/613553 [patent_app_country] => US [patent_app_date] => 2003-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5219 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20040069529.pdf [firstpage_image] =>[orig_patent_app_number] => 10613553 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/613553
Coaxial via structure for optimizing signal transmission in multiple layer electronic device carriers Jul 1, 2003 Issued
Array ( [id] => 7400629 [patent_doc_number] => 20040262039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Bond finger on via substrate, process of making same, package made thereby, and method of assembling same' [patent_app_type] => new [patent_app_number] => 10/612281 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5453 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262039.pdf [firstpage_image] =>[orig_patent_app_number] => 10612281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612281
Bond finger on via substrate, process of making same, package made thereby, and method of assembling same Jun 29, 2003 Issued
Array ( [id] => 341826 [patent_doc_number] => 07501584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Circuit board device and method for board-to-board connection' [patent_app_type] => utility [patent_app_number] => 10/519002 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5869 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501584.pdf [firstpage_image] =>[orig_patent_app_number] => 10519002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/519002
Circuit board device and method for board-to-board connection Jun 23, 2003 Issued
Array ( [id] => 7322670 [patent_doc_number] => 20040251047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Via structure for increased wiring on printed wiring boards' [patent_app_type] => new [patent_app_number] => 10/460591 [patent_app_country] => US [patent_app_date] => 2003-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5012 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251047.pdf [firstpage_image] =>[orig_patent_app_number] => 10460591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460591
Via structure for increased wiring on printed wiring boards Jun 11, 2003 Abandoned
Array ( [id] => 6727220 [patent_doc_number] => 20030183410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Superconducting cable' [patent_app_type] => new [patent_app_number] => 10/363008 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13497 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183410.pdf [firstpage_image] =>[orig_patent_app_number] => 10363008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/363008
Superconducting cable Jun 8, 2003 Abandoned
Array ( [id] => 6767676 [patent_doc_number] => 20030213616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Printed wiring board and electronic device using the same' [patent_app_type] => new [patent_app_number] => 10/437901 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5594 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20030213616.pdf [firstpage_image] =>[orig_patent_app_number] => 10437901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437901
Printed wiring board and electronic device using the same May 14, 2003 Issued
Array ( [id] => 7423290 [patent_doc_number] => 20040229396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Multilayer flip-chip substrate interconnect layout' [patent_app_type] => new [patent_app_number] => 10/438238 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4548 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20040229396.pdf [firstpage_image] =>[orig_patent_app_number] => 10438238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438238
Multilayer flip-chip substrate interconnect layout May 13, 2003 Issued
Array ( [id] => 521250 [patent_doc_number] => 07189927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Electronic component with bump electrodes, and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/434151 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 10673 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/189/07189927.pdf [firstpage_image] =>[orig_patent_app_number] => 10434151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434151
Electronic component with bump electrodes, and manufacturing method thereof May 8, 2003 Issued
Array ( [id] => 7417578 [patent_doc_number] => 20040182604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Pinned electronic package with strengthened conductive pad' [patent_app_type] => new [patent_app_number] => 10/423972 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4673 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20040182604.pdf [firstpage_image] =>[orig_patent_app_number] => 10423972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423972
Pinned electronic package with strengthened conductive pad Apr 27, 2003 Issued
Array ( [id] => 7629521 [patent_doc_number] => 06818835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Processor and power supply circuit' [patent_app_type] => B2 [patent_app_number] => 10/420572 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8890 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818835.pdf [firstpage_image] =>[orig_patent_app_number] => 10420572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420572
Processor and power supply circuit Apr 21, 2003 Issued
Array ( [id] => 923225 [patent_doc_number] => 07319197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Structure of stacked vias in multiple layer electrode device carriers' [patent_app_type] => utility [patent_app_number] => 10/515511 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4783 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319197.pdf [firstpage_image] =>[orig_patent_app_number] => 10515511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/515511
Structure of stacked vias in multiple layer electrode device carriers Apr 17, 2003 Issued
Array ( [id] => 518430 [patent_doc_number] => 07193158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Wiring board device' [patent_app_type] => utility [patent_app_number] => 10/414000 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193158.pdf [firstpage_image] =>[orig_patent_app_number] => 10414000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414000
Wiring board device Apr 15, 2003 Issued
Array ( [id] => 8283172 [patent_doc_number] => 08217276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Multilayer printed circuit board and method of manufacturing multilayer printed circuit board' [patent_app_type] => utility [patent_app_number] => 10/410434 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 6959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10410434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410434
Multilayer printed circuit board and method of manufacturing multilayer printed circuit board Apr 9, 2003 Issued
Array ( [id] => 404890 [patent_doc_number] => 07288723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Circuit board including isolated signal transmission channels' [patent_app_type] => utility [patent_app_number] => 10/405440 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3222 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288723.pdf [firstpage_image] =>[orig_patent_app_number] => 10405440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405440
Circuit board including isolated signal transmission channels Apr 1, 2003 Issued
Array ( [id] => 6845080 [patent_doc_number] => 20030164247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Stacking multiple devices using direct soldering' [patent_app_type] => new [patent_app_number] => 10/404266 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2509 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20030164247.pdf [firstpage_image] =>[orig_patent_app_number] => 10404266 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404266
Stacking multiple devices using direct soldering Mar 31, 2003 Abandoned
Array ( [id] => 537566 [patent_doc_number] => 07173193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Method and structure for implementing enhanced interconnection performance of a land grid array (LGA) module and a printed wiring board' [patent_app_type] => utility [patent_app_number] => 10/403148 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3655 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173193.pdf [firstpage_image] =>[orig_patent_app_number] => 10403148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403148
Method and structure for implementing enhanced interconnection performance of a land grid array (LGA) module and a printed wiring board Mar 30, 2003 Issued
Menu