Jerome D Goldberg

Array ( [id] => 1318965 [patent_doc_number] => 06618783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method and system for managing a PCI bus coupled to another system' [patent_app_type] => B1 [patent_app_number] => 09/430369 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618783.pdf [firstpage_image] =>[orig_patent_app_number] => 09430369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178812 [patent_doc_number] => 06757762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Multi-mode processor bus bridge' [patent_app_type] => B1 [patent_app_number] => 09/430314 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1513 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757762.pdf [firstpage_image] =>[orig_patent_app_number] => 09430314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1438647 [patent_doc_number] => 06356967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Adding plug-in unit slots to a high capacity bus' [patent_app_type] => B1 [patent_app_number] => 09/420663 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4131 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356967.pdf [firstpage_image] =>[orig_patent_app_number] => 09420663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431364 [patent_doc_number] => 06519666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Arbitration scheme for optimal performance' [patent_app_type] => B1 [patent_app_number] => 09/412990 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7225 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519666.pdf [firstpage_image] =>[orig_patent_app_number] => 09412990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1221695 [patent_doc_number] => 06708245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Interface circuit with improved integration' [patent_app_type] => B1 [patent_app_number] => 09/412753 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6059 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708245.pdf [firstpage_image] =>[orig_patent_app_number] => 09412753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631579 [patent_doc_number] => 06665758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Software sanity monitor' [patent_app_type] => B1 [patent_app_number] => 09/411497 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5074 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665758.pdf [firstpage_image] =>[orig_patent_app_number] => 09411497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248811 [patent_doc_number] => 06678780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method and apparatus for supporting multiple bus masters with the accelerated graphics protocol (AGP) bus' [patent_app_type] => B1 [patent_app_number] => 09/411661 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2857 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678780.pdf [firstpage_image] =>[orig_patent_app_number] => 09411661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1225469 [patent_doc_number] => 06704822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Arbitration protocol for a shared data cache' [patent_app_type] => B1 [patent_app_number] => 09/411470 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9136 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704822.pdf [firstpage_image] =>[orig_patent_app_number] => 09411470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1296994 [patent_doc_number] => 06633942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Distributed real-time operating system providing integrated interrupt management' [patent_app_type] => B1 [patent_app_number] => 09/408670 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7666 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633942.pdf [firstpage_image] =>[orig_patent_app_number] => 09408670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1192412 [patent_doc_number] => 06735655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Interrupt request controller' [patent_app_type] => B1 [patent_app_number] => 09/408430 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 8001 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735655.pdf [firstpage_image] =>[orig_patent_app_number] => 09408430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1092787 [patent_doc_number] => 06829666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Modular computing architecture having common communication interface' [patent_app_type] => B1 [patent_app_number] => 09/408874 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 4399 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829666.pdf [firstpage_image] =>[orig_patent_app_number] => 09408874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1400749 [patent_doc_number] => 06564279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus facilitating insertion and removal of modules in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/408735 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6495 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564279.pdf [firstpage_image] =>[orig_patent_app_number] => 09408735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297017 [patent_doc_number] => 06633946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Flexible switch-based I/O system interconnect' [patent_app_type] => B1 [patent_app_number] => 09/408390 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4130 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633946.pdf [firstpage_image] =>[orig_patent_app_number] => 09408390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587305 [patent_doc_number] => 06425030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Serial data-and control-bus with distribution voltage' [patent_app_type] => B1 [patent_app_number] => 09/284363 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4842 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425030.pdf [firstpage_image] =>[orig_patent_app_number] => 09284363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630019 [patent_doc_number] => 06636920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Enhanced bus connectivity through distributed loading' [patent_app_type] => B1 [patent_app_number] => 09/384665 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2382 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636920.pdf [firstpage_image] =>[orig_patent_app_number] => 09384665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1325050 [patent_doc_number] => 06615305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Interrupt pacing in data transfer unit' [patent_app_type] => B1 [patent_app_number] => 09/384494 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615305.pdf [firstpage_image] =>[orig_patent_app_number] => 09384494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1357367 [patent_doc_number] => 06591368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and apparatus for controlling power of computer system using wake up LAN (local area network) signal' [patent_app_type] => B1 [patent_app_number] => 09/363658 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2924 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591368.pdf [firstpage_image] =>[orig_patent_app_number] => 09363658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210323 [patent_doc_number] => 06718422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Enhanced bus arbiter utilizing variable priority and fairness' [patent_app_type] => B1 [patent_app_number] => 09/363947 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5103 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718422.pdf [firstpage_image] =>[orig_patent_app_number] => 09363947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279323 [patent_doc_number] => 06654833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Bus arbitration' [patent_app_type] => B1 [patent_app_number] => 09/363547 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2944 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654833.pdf [firstpage_image] =>[orig_patent_app_number] => 09363547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169395 [patent_doc_number] => 06763416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Capturing read data' [patent_app_type] => B1 [patent_app_number] => 09/363605 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3301 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763416.pdf [firstpage_image] =>[orig_patent_app_number] => 09363605 [rel_patent_id] =>[rel_patent_doc_number] =>)