Jerome D Goldberg

Array ( [id] => 4279510 [patent_doc_number] => 06205501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Apparatus and method for handling universal serial bus control transfers' [patent_app_type] => 1 [patent_app_number] => 9/004002 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9445 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205501.pdf [firstpage_image] =>[orig_patent_app_number] => 004002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495230 [patent_doc_number] => 06418493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for robust addressing on a dynamically configurable bus' [patent_app_type] => B1 [patent_app_number] => 08/998583 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2929 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418493.pdf [firstpage_image] =>[orig_patent_app_number] => 08998583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291925 [patent_doc_number] => 06247079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Apparatus for computer implemented hot-swap and hot-add' [patent_app_type] => 1 [patent_app_number] => 8/942282 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14836 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247079.pdf [firstpage_image] =>[orig_patent_app_number] => 942282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3755565 [patent_doc_number] => 05787260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Busline length recognition system' [patent_app_type] => 1 [patent_app_number] => 8/934887 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3438 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787260.pdf [firstpage_image] =>[orig_patent_app_number] => 934887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4048270 [patent_doc_number] => 05857116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Circuit for disabling an address masking control signal when a microprocessor is in a system management mode' [patent_app_type] => 1 [patent_app_number] => 8/918838 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857116.pdf [firstpage_image] =>[orig_patent_app_number] => 918838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969929 [patent_doc_number] => 05958032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Data processing and communicating system with high throughput peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/895984 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3460 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958032.pdf [firstpage_image] =>[orig_patent_app_number] => 895984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3997168 [patent_doc_number] => 05961627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'High speed switch for high speed connection between computers and peripheral devices' [patent_app_type] => 1 [patent_app_number] => 8/878081 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1050 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961627.pdf [firstpage_image] =>[orig_patent_app_number] => 878081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042490 [patent_doc_number] => 05931933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Apparatus and method for communication and translation for selected one of a variety of data bus formats' [patent_app_type] => 1 [patent_app_number] => 8/877014 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931933.pdf [firstpage_image] =>[orig_patent_app_number] => 877014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915753 [patent_doc_number] => 05944831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Power management apparatus and method for managing power application to individual circuit cards' [patent_app_type] => 1 [patent_app_number] => 8/874493 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3951 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944831.pdf [firstpage_image] =>[orig_patent_app_number] => 874493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042187 [patent_doc_number] => 05903737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Apparatus and method for serial data communication utilizing general microcomputer' [patent_app_type] => 1 [patent_app_number] => 8/865779 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2118 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903737.pdf [firstpage_image] =>[orig_patent_app_number] => 865779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3945100 [patent_doc_number] => 05935233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Computer system with a switch interconnector for computer devices' [patent_app_type] => 1 [patent_app_number] => 8/859894 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5740 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935233.pdf [firstpage_image] =>[orig_patent_app_number] => 859894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042706 [patent_doc_number] => 05931949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Expansion port providing system power-down prior to connection of peripheral devices' [patent_app_type] => 1 [patent_app_number] => 8/859833 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3655 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931949.pdf [firstpage_image] =>[orig_patent_app_number] => 859833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4017906 [patent_doc_number] => 05859989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/855341 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6917 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859989.pdf [firstpage_image] =>[orig_patent_app_number] => 855341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4047789 [patent_doc_number] => 05857086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/855401 [patent_app_country] => US [patent_app_date] => 1997-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6829 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/857/05857086.pdf [firstpage_image] =>[orig_patent_app_number] => 855401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924127 [patent_doc_number] => 05938769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'CPU escalating adapter with multivoltage and multiple frequency selection' [patent_app_type] => 1 [patent_app_number] => 8/845149 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1666 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938769.pdf [firstpage_image] =>[orig_patent_app_number] => 845149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076521 [patent_doc_number] => 05896539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities' [patent_app_type] => 1 [patent_app_number] => 8/839438 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3504 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896539.pdf [firstpage_image] =>[orig_patent_app_number] => 839438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3830762 [patent_doc_number] => 05812859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Information processing apparatus with work suspend/resume function' [patent_app_type] => 1 [patent_app_number] => 8/835511 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812859.pdf [firstpage_image] =>[orig_patent_app_number] => 835511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015127 [patent_doc_number] => 05925119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Computer architecture for automated storage library' [patent_app_type] => 1 [patent_app_number] => 8/828438 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6428 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925119.pdf [firstpage_image] =>[orig_patent_app_number] => 828438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3987586 [patent_doc_number] => 05922059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Circuit board connector' [patent_app_type] => 1 [patent_app_number] => 8/818751 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5013 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922059.pdf [firstpage_image] =>[orig_patent_app_number] => 818751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4068680 [patent_doc_number] => 05970234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'PCI bus arbiter and a bus control system having the same' [patent_app_type] => 1 [patent_app_number] => 8/792424 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9595 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970234.pdf [firstpage_image] =>[orig_patent_app_number] => 792424 [rel_patent_id] =>[rel_patent_doc_number] =>)