Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20019299 [patent_doc_number] => 20250157521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories [patent_app_type] => utility [patent_app_number] => 19/022183 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19022183 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/022183
Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories Jan 14, 2025 Pending
Array ( [id] => 19820707 [patent_doc_number] => 20250078914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MULTIPLE LAYER DUAL PORT MEMORY CELL MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/952719 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952719
MULTIPLE LAYER DUAL PORT MEMORY CELL MANUFACTURING METHOD Nov 18, 2024 Pending
Array ( [id] => 19802435 [patent_doc_number] => 20250068360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/943644 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943644
APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS Nov 10, 2024 Pending
Array ( [id] => 20710559 [patent_doc_number] => 20260134897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-14 [patent_title] => SELECTIVE ENABLING AND DISABLING OF SENSE AMPLIFIER CIRCUITRIES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/943561 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943561
SELECTIVE ENABLING AND DISABLING OF SENSE AMPLIFIER CIRCUITRIES IN A MEMORY DEVICE Nov 10, 2024 Pending
Array ( [id] => 19803711 [patent_doc_number] => 20250069636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => FLASH MEMORY DEVICES INCLUDING DRAM [patent_app_type] => utility [patent_app_number] => 18/939609 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939609
FLASH MEMORY DEVICES INCLUDING DRAM Nov 6, 2024 Pending
Array ( [id] => 19757817 [patent_doc_number] => 20250046382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 18/926712 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926712
SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SENSE AMPLIFIERS Oct 24, 2024 Pending
Array ( [id] => 19893060 [patent_doc_number] => 20250118372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN [patent_app_type] => utility [patent_app_number] => 18/913710 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913710
WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN Oct 10, 2024 Pending
Array ( [id] => 20915160 [patent_doc_number] => 12712014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Vertical memory device with a double word line structure [patent_app_type] => utility [patent_app_number] => 18/911271 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6594 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/911271
VERTICAL MEMORY DEVICE WITH A DOUBLE WORD LINE STRUCTURE Oct 9, 2024 Pending
Array ( [id] => 20381553 [patent_doc_number] => 20250364046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/904197 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904197 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904197
MEMORY DEVICE Oct 1, 2024 Pending
Array ( [id] => 20630355 [patent_doc_number] => 20260094643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => READ SIGNAL OUTPUT TERMINAL DRIVER [patent_app_type] => utility [patent_app_number] => 18/904495 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904495
READ SIGNAL OUTPUT TERMINAL DRIVER Oct 1, 2024 Pending
Array ( [id] => 19893078 [patent_doc_number] => 20250118390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => TEST DEVICE, OPERATING METHOD OF THE SAME, AND TEST SYSTEM [patent_app_type] => utility [patent_app_number] => 18/904629 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904629
TEST DEVICE, OPERATING METHOD OF THE SAME, AND TEST SYSTEM Oct 1, 2024 Pending
Array ( [id] => 20253048 [patent_doc_number] => 20250301917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/894421 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/894421
MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME Sep 23, 2024 Pending
Array ( [id] => 20884390 [patent_doc_number] => 12700434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/828820 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828820 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828820
SEMICONDUCTOR MEMORY DEVICE Sep 8, 2024 Pending
Array ( [id] => 19636477 [patent_doc_number] => 20240414926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING CHALCOGEN COMPOUND AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/813539 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813539
SEMICONDUCTOR DEVICE INCLUDING CHALCOGEN COMPOUND AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME Aug 22, 2024 Pending
Array ( [id] => 20053421 [patent_doc_number] => 20250191643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => SEMICONDUCTOR DEVICE HAVING DELAY LINE [patent_app_type] => utility [patent_app_number] => 18/780165 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780165
SEMICONDUCTOR DEVICE HAVING DELAY LINE Jul 21, 2024 Pending
Array ( [id] => 20002085 [patent_doc_number] => 20250140307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => BIT LINE PRE-CHARGE VOLTAGE GENERATING CIRCUIT IN SEMICONDUCTOR MEMORY DEVICES FOR REDUCING CURRENT CONSUMPTION [patent_app_type] => utility [patent_app_number] => 18/778336 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778336
Bit line pre-charge voltage generating circuit in semiconductor memory devices for reducing current consumption Jul 18, 2024 Issued
Array ( [id] => 19559630 [patent_doc_number] => 20240371422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DATA RECEIVING CIRCUIT FOR CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/773410 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773410 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773410
DATA RECEIVING CIRCUIT FOR CHIPLET BASED STORAGE ARCHITECTURES Jul 14, 2024 Pending
Array ( [id] => 20806048 [patent_doc_number] => 12670960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Memory device for applying voltages to word lines during erase operations and operating method for memory device [patent_app_type] => utility [patent_app_number] => 18/761315 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761315
Memory device for applying voltages to word lines during erase operations and operating method for memory device Jul 1, 2024 Issued
Array ( [id] => 20102854 [patent_doc_number] => 20250232790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => RACETRACK MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/760609 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760609
RACETRACK MEMORY DEVICE Jun 30, 2024 Pending
Array ( [id] => 20448122 [patent_doc_number] => 20260004847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => PROGRESSIVE SEASONING FOR THRESHOLD SWITCHING SELECTORS [patent_app_type] => utility [patent_app_number] => 18/756373 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756373
PROGRESSIVE SEASONING FOR THRESHOLD SWITCHING SELECTORS Jun 26, 2024 Pending
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