Jerome Larry Leboeuf

Array ( [id] => 18623575 [patent_doc_number] => 11756628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor memory device with first and second sense amplifiers [patent_app_type] => utility [patent_app_number] => 17/326954 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 32409 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17745438 [patent_doc_number] => 11393517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Apparatus and methods for writing random access memories [patent_app_type] => utility [patent_app_number] => 17/319991 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486350 [patent_doc_number] => 20220093854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ELECTRONIC SYNAPTIC DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/315434 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19980021 [patent_doc_number] => 12347507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Method and apparatus for memory chip row hammer threat backpressure signal and host side response [patent_app_type] => utility [patent_app_number] => 17/315303 [patent_app_country] => US [patent_app_date] => 2021-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2237 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17993785 [patent_doc_number] => 20220359822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ELECTRODE STRUCTURES FOR MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/315114 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18768475 [patent_doc_number] => 11818899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor device including layers with different chalcogen compounds and semiconductor apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/244212 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10082 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19288337 [patent_doc_number] => 20240224820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => MEMRISTOR, METHOD OF CALCULATING HAMMING DISTANCE, AND IN-MEMORY COMPUTING INTEGRATION APPLICATION [patent_app_type] => utility [patent_app_number] => 18/287462 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18287462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17709099 [patent_doc_number] => 20220209107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => CMOS-COMPATIBLE PROTONIC RESISTIVE DEVICES [patent_app_type] => utility [patent_app_number] => 17/627160 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17627160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17339538 [patent_doc_number] => 20220005869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/232865 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19906552 [patent_doc_number] => 12283571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-22 [patent_title] => Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor [patent_app_type] => utility [patent_app_number] => 17/230889 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 29 [patent_no_of_words] => 8004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17417209 [patent_doc_number] => 20220052113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE MATERIAL PATTERN AND SELECTOR MATERIAL PATTERN [patent_app_type] => utility [patent_app_number] => 17/220998 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17583383 [patent_doc_number] => 20220140238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/220271 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18359264 [patent_doc_number] => 11647684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Nonvolatile tunable capacitive processing unit [patent_app_type] => utility [patent_app_number] => 17/216937 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9780 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115763 [patent_doc_number] => 20210296360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => THREE DIMENSIONAL DOUBLE-DENSITY MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/209109 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19844122 [patent_doc_number] => 12256538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Anti-fuse unit structure and anti-fuse array [patent_app_type] => utility [patent_app_number] => 17/310859 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3520 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17855571 [patent_doc_number] => 20220285614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => INTEGRATED SWITCH USING STACKED PHASE CHANGE MATERIALS [patent_app_type] => utility [patent_app_number] => 17/192223 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17192223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17529708 [patent_doc_number] => 11302406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Array of nor memory strings and system for rapid data retrieval [patent_app_type] => utility [patent_app_number] => 17/187601 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 32457 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19231279 [patent_doc_number] => 12010934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Selection element with a plurality of amorphous layers [patent_app_type] => utility [patent_app_number] => 17/168686 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17780497 [patent_doc_number] => 20220246847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => ELEMENTAL COMPOSITION TUNING FOR CHALCOGENIDE BASED MEMORY [patent_app_type] => utility [patent_app_number] => 17/163155 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18774008 [patent_doc_number] => 20230368838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => MEMORY CIRCUIT STRUCTURE AND METHOD OF OPERATING MEMORY CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/247213 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18247213 [rel_patent_id] =>[rel_patent_doc_number] =>)