
Jerome Larry Leboeuf
Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 617 |
| Issued Applications | 492 |
| Pending Applications | 62 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17925676
[patent_doc_number] => 11468935
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Memory system having combined high density, low bandwidth and low density, high bandwidth memories
[patent_app_type] => utility
[patent_app_number] => 17/140753
[patent_app_country] => US
[patent_app_date] => 2021-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5205
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140753
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/140753 | Memory system having combined high density, low bandwidth and low density, high bandwidth memories | Jan 3, 2021 | Issued |
Array
(
[id] => 16782037
[patent_doc_number] => 20210119116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SPACER STACK FOR MAGNETIC TUNNEL JUNCTIONS
[patent_app_type] => utility
[patent_app_number] => 17/135637
[patent_app_country] => US
[patent_app_date] => 2020-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5739
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135637
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/135637 | Methods for forming a spacer stack for magnetic tunnel junctions | Dec 27, 2020 | Issued |
Array
(
[id] => 17115803
[patent_doc_number] => 20210296400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/125126
[patent_app_country] => US
[patent_app_date] => 2020-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8935
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125126
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/125126 | Memory device with a plurality of metal chalcogenide layers | Dec 16, 2020 | Issued |
Array
(
[id] => 17676405
[patent_doc_number] => 20220189572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => DATA INTEGRITY CHECKS BASED ON VOLTAGE DISTRIBUTION METRICS
[patent_app_type] => utility
[patent_app_number] => 17/123993
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9894
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123993
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/123993 | Data integrity checks based on voltage distribution metrics | Dec 15, 2020 | Issued |
Array
(
[id] => 18529844
[patent_doc_number] => 11716861
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-01
[patent_title] => Electrically formed memory array using single element materials
[patent_app_type] => utility
[patent_app_number] => 17/122464
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6789
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122464
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/122464 | Electrically formed memory array using single element materials | Dec 14, 2020 | Issued |
Array
(
[id] => 17677072
[patent_doc_number] => 20220190239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => IN-MEMORY RESISTIVE RANDOM ACCESS MEMORY XOR LOGIC USING COMPLIMENTARY SWITCHING
[patent_app_type] => utility
[patent_app_number] => 17/122800
[patent_app_country] => US
[patent_app_date] => 2020-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3191
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122800
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/122800 | In-memory resistive random access memory XOR logic using complimentary switching | Dec 14, 2020 | Issued |
Array
(
[id] => 17661083
[patent_doc_number] => 20220181548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => SYSTEM AND DEVICE INCLUDING MEMRISTOR MATERIAL
[patent_app_type] => utility
[patent_app_number] => 17/113406
[patent_app_country] => US
[patent_app_date] => 2020-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113406
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/113406 | System and device including memristor material | Dec 6, 2020 | Issued |
Array
(
[id] => 17645570
[patent_doc_number] => 20220173309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => PHASE-CHANGE MATERIAL-BASED XOR LOGIC GATES
[patent_app_type] => utility
[patent_app_number] => 17/108277
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7990
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108277
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108277 | Phase-change material-based XOR logic gates | Nov 30, 2020 | Issued |
Array
(
[id] => 17716383
[patent_doc_number] => 11380381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Techniques and devices for canceling memory cell variations
[patent_app_type] => utility
[patent_app_number] => 17/108801
[patent_app_country] => US
[patent_app_date] => 2020-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 16410
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108801
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/108801 | Techniques and devices for canceling memory cell variations | Nov 30, 2020 | Issued |
Array
(
[id] => 16660778
[patent_doc_number] => 20210057415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => Thyristor Volatile Random Access Memory and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 17/090742
[patent_app_country] => US
[patent_app_date] => 2020-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6591
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090742
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/090742 | Thyristor volatile random access memory and methods of manufacture | Nov 4, 2020 | Issued |
Array
(
[id] => 17438759
[patent_doc_number] => 11264099
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-01
[patent_title] => Apparatuses and methods for automated dynamic word line start voltage
[patent_app_type] => utility
[patent_app_number] => 17/090067
[patent_app_country] => US
[patent_app_date] => 2020-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 11086
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090067
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/090067 | Apparatuses and methods for automated dynamic word line start voltage | Nov 4, 2020 | Issued |
Array
(
[id] => 16659380
[patent_doc_number] => 20210056017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => APPARATUSES AND METHODS FOR MEMORY DEVICE AS A STORE FOR PROGRAM INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 17/080495
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11303
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080495
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080495 | Apparatuses and methods for memory device as a store for program instructions | Oct 25, 2020 | Issued |
Array
(
[id] => 17551867
[patent_doc_number] => 20220123209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => SELECTOR DEVICES INCLUDING S-DOPED AsSeGeSi CHALCOGENIDES
[patent_app_type] => utility
[patent_app_number] => 17/072906
[patent_app_country] => US
[patent_app_date] => 2020-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4499
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072906
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/072906 | SELECTOR DEVICES INCLUDING S-DOPED AsSeGeSi CHALCOGENIDES | Oct 15, 2020 | Abandoned |
Array
(
[id] => 18825485
[patent_doc_number] => 11840756
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-12
[patent_title] => Binary Ag--Cu amorphous thin-films for electronic applications
[patent_app_type] => utility
[patent_app_number] => 17/066670
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 5801
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066670
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/066670 | Binary Ag--Cu amorphous thin-films for electronic applications | Oct 8, 2020 | Issued |
Array
(
[id] => 17757290
[patent_doc_number] => 11397582
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => NAND type lookup-table hardware search engine
[patent_app_type] => utility
[patent_app_number] => 17/038759
[patent_app_country] => US
[patent_app_date] => 2020-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 5034
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 701
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038759
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/038759 | NAND type lookup-table hardware search engine | Sep 29, 2020 | Issued |
Array
(
[id] => 16920569
[patent_doc_number] => 20210193661
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/032040
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032040
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/032040 | Memory devices with vertical channels | Sep 24, 2020 | Issued |
Array
(
[id] => 17047805
[patent_doc_number] => 11100995
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Structure of a nonvolatile memory device with a low-voltage transistor fabricated on a substrate
[patent_app_type] => utility
[patent_app_number] => 17/030124
[patent_app_country] => US
[patent_app_date] => 2020-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3224
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030124
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030124 | Structure of a nonvolatile memory device with a low-voltage transistor fabricated on a substrate | Sep 22, 2020 | Issued |
Array
(
[id] => 17485700
[patent_doc_number] => 20220093204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => LOW POWER MEMORY STATE RETENTION REGULATOR
[patent_app_type] => utility
[patent_app_number] => 17/030134
[patent_app_country] => US
[patent_app_date] => 2020-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3723
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030134
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030134 | Low power memory state retention regulator | Sep 22, 2020 | Issued |
Array
(
[id] => 16578828
[patent_doc_number] => 20210013229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/028748
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12314
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028748 | Semiconductor memory device incorporating hafnium oxide insulative portions | Sep 21, 2020 | Issued |
Array
(
[id] => 17477114
[patent_doc_number] => 20220084618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => SYSTEMS AND METHODS FOR USING COLUMN REDUNDANCY FOR ERROR BIT DETECTION AND CORRECTION
[patent_app_type] => utility
[patent_app_number] => 17/023958
[patent_app_country] => US
[patent_app_date] => 2020-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10239
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023958
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/023958 | SYSTEMS AND METHODS FOR USING COLUMN REDUNDANCY FOR ERROR BIT DETECTION AND CORRECTION | Sep 16, 2020 | Abandoned |