Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17137475 [patent_doc_number] => 11139040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Method of detecting address decoding error [patent_app_type] => utility [patent_app_number] => 16/777566 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/777566
Method of detecting address decoding error Jan 29, 2020 Issued
Array ( [id] => 15967313 [patent_doc_number] => 20200167408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => VECTOR-BY-MATRIX MULTIPLIER MODULES BASED ON NON-VOLATILE 2D AND 3D MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/777626 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/777626
VECTOR-BY-MATRIX MULTIPLIER MODULES BASED ON NON-VOLATILE 2D AND 3D MEMORY ARRAYS Jan 29, 2020 Abandoned
Array ( [id] => 17047784 [patent_doc_number] => 11100974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path [patent_app_type] => utility [patent_app_number] => 16/689900 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689900
Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path Jan 14, 2020 Issued
Array ( [id] => 16180154 [patent_doc_number] => 20200227123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => IMPLEMENTING LOGIC FUNCTION AND GENERATING ANALOG SIGNALS USING NOR MEMORY STRINGS [patent_app_type] => utility [patent_app_number] => 16/744067 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744067
Implementing logic function and generating analog signals using NOR memory strings Jan 14, 2020 Issued
Array ( [id] => 16194258 [patent_doc_number] => 20200235107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => ANTIFUSE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/742886 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742886
ANTIFUSE MEMORY CELLS Jan 13, 2020 Abandoned
Array ( [id] => 16516154 [patent_doc_number] => 20200395412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD OF OPERATING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/734937 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734937
Semiconductor device with first and second data structures Jan 5, 2020 Issued
Array ( [id] => 15872925 [patent_doc_number] => 20200143866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories [patent_app_type] => utility [patent_app_number] => 16/734595 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734595
Memory system having combined high density, low bandwidth and low density, high bandwidth memories Jan 5, 2020 Issued
Array ( [id] => 18000716 [patent_doc_number] => 11501827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Vertical memory device with a double word line structure [patent_app_type] => utility [patent_app_number] => 16/728174 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728174
Vertical memory device with a double word line structure Dec 26, 2019 Issued
Array ( [id] => 16936945 [patent_doc_number] => 20210202834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => PHASE-CHANGE MEMORY AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 16/727155 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727155
Phase-change memory with two-portioned phase-change layer Dec 25, 2019 Issued
Array ( [id] => 16959331 [patent_doc_number] => 11063215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Spacial arrangments of and critical dimensions for bit line contacts of three-dimensional phase-change memory devices [patent_app_type] => utility [patent_app_number] => 16/727852 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 12188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727852
Spacial arrangments of and critical dimensions for bit line contacts of three-dimensional phase-change memory devices Dec 25, 2019 Issued
Array ( [id] => 17181536 [patent_doc_number] => 11158787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => C--As--Se--Ge ovonic materials for selector devices and memory devices using same [patent_app_type] => utility [patent_app_number] => 16/716948 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716948
C--As--Se--Ge ovonic materials for selector devices and memory devices using same Dec 16, 2019 Issued
Array ( [id] => 15806929 [patent_doc_number] => 20200126607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => METHOD AND CIRCUIT ENABLING FERROELECTRIC MEMORY TO BE FIXED TO A STABLE STATE [patent_app_type] => utility [patent_app_number] => 16/716870 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716870
METHOD AND CIRCUIT ENABLING FERROELECTRIC MEMORY TO BE FIXED TO A STABLE STATE Dec 16, 2019 Abandoned
Array ( [id] => 17638332 [patent_doc_number] => 11349069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Resistive memory devices using a carbon-based conductor line and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/715216 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 53 [patent_no_of_words] => 11505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715216
Resistive memory devices using a carbon-based conductor line and methods for forming the same Dec 15, 2019 Issued
Array ( [id] => 15772713 [patent_doc_number] => 20200117374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/715751 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715751
Memory system for increasing a read reclaim count Dec 15, 2019 Issued
Array ( [id] => 17194730 [patent_doc_number] => 11163483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Robust detection techniques for updating read voltages of memory devices [patent_app_type] => utility [patent_app_number] => 16/707381 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16707381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/707381
Robust detection techniques for updating read voltages of memory devices Dec 8, 2019 Issued
Array ( [id] => 17493701 [patent_doc_number] => 11283019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Resistance random access memory device and fabricating method of the same [patent_app_type] => utility [patent_app_number] => 16/704116 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6404 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704116
Resistance random access memory device and fabricating method of the same Dec 4, 2019 Issued
Array ( [id] => 16858648 [patent_doc_number] => 20210159393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => MAGNETIC TUNNEL JUNCTION DEVICES AND METHODS OF FORMING THEREOF [patent_app_type] => utility [patent_app_number] => 16/695333 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695333 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695333
MAGNETIC TUNNEL JUNCTION DEVICES AND METHODS OF FORMING THEREOF Nov 25, 2019 Abandoned
Array ( [id] => 16394213 [patent_doc_number] => 20200335154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/692687 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692687
MEMORY DEVICE Nov 21, 2019 Abandoned
Array ( [id] => 17359961 [patent_doc_number] => 20220020757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND NEURAL NETWORK DEVICE [patent_app_type] => utility [patent_app_number] => 17/309597 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17309597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/309597
Semiconductor storage device using two insulative storage elements and neural network device using the same Nov 20, 2019 Issued
Array ( [id] => 19198884 [patent_doc_number] => 11996132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Three transistor semiconductor device with metal oxide channel region, operation method thereof, and electronic device [patent_app_type] => utility [patent_app_number] => 17/298964 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 23363 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17298964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/298964
Three transistor semiconductor device with metal oxide channel region, operation method thereof, and electronic device Nov 19, 2019 Issued
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