Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16424805 [patent_doc_number] => 20200350003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => Signal Communication Circuit Implementing Receiver and Trasmitter Circuits [patent_app_type] => utility [patent_app_number] => 16/399921 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399921
Signal communication circuit implementing receiver and transmitter circuits Apr 29, 2019 Issued
Array ( [id] => 14784321 [patent_doc_number] => 20190267058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/373345 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16373345 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/373345
Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code Apr 1, 2019 Issued
Array ( [id] => 16723951 [patent_doc_number] => 20210091098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/975024 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/975024
SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS Mar 31, 2019 Abandoned
Array ( [id] => 14587325 [patent_doc_number] => 20190221271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => OPERATION METHOD FOR SUPPRESSING FLOATING GATE (FG) COUPLING [patent_app_type] => utility [patent_app_number] => 16/361258 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16361258 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/361258
Operation method for suppressing floating gate (FG) coupling Mar 21, 2019 Issued
Array ( [id] => 14570625 [patent_doc_number] => 20190212919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => HYBRID MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/358219 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358219
Hybrid memory device using different types of capacitors and operating method thereof Mar 18, 2019 Issued
Array ( [id] => 16463884 [patent_doc_number] => 10847241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Joint soft boundaries and LLRS update for flash memory [patent_app_type] => utility [patent_app_number] => 16/299179 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5013 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299179
Joint soft boundaries and LLRS update for flash memory Mar 11, 2019 Issued
Array ( [id] => 15442231 [patent_doc_number] => 20200035299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => METHOD AND SYSTEM FOR POWER LOSS PROTECTION [patent_app_type] => utility [patent_app_number] => 16/296241 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/296241
METHOD AND SYSTEM FOR POWER LOSS PROTECTION Mar 7, 2019 Abandoned
Array ( [id] => 16698502 [patent_doc_number] => 10949099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Memory system for adjusting read reclaim counts and method for operating the same [patent_app_type] => utility [patent_app_number] => 16/289173 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 12223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289173 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289173
Memory system for adjusting read reclaim counts and method for operating the same Feb 27, 2019 Issued
Array ( [id] => 16545344 [patent_doc_number] => 20200411759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SWITCH DEVICE, STORAGE APPARATUS, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/975630 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16975630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/975630
Switch device, storage apparatus, and memory system incorporating boron and carbon Jan 30, 2019 Issued
Array ( [id] => 14381323 [patent_doc_number] => 20190164574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => ERROR DETECTION CODE HOLD PATTERN SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 16/262661 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262661
Error detection code hold pattern synchronization Jan 29, 2019 Issued
Array ( [id] => 14349845 [patent_doc_number] => 20190156895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SYSTEM, APPARATUS, AND METHOD OF PROGRAMMING A ONE-TIME PROGRAMMABLE MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/260026 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/260026
SYSTEM, APPARATUS, AND METHOD OF PROGRAMMING A ONE-TIME PROGRAMMABLE MEMORY CIRCUIT Jan 27, 2019 Abandoned
Array ( [id] => 15473265 [patent_doc_number] => 10552510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Vector-by-matrix multiplier modules based on non-volatile 2D and 3D memory arrays [patent_app_type] => utility [patent_app_number] => 16/246353 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16141 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246353
Vector-by-matrix multiplier modules based on non-volatile 2D and 3D memory arrays Jan 10, 2019 Issued
Array ( [id] => 16120065 [patent_doc_number] => 20200212055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => INTEGRATION SCHEME FOR FERROELECTRIC MEMORY WITH A DEEP TRENCH STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/236047 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236047 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236047
INTEGRATION SCHEME FOR FERROELECTRIC MEMORY WITH A DEEP TRENCH STRUCTURE Dec 27, 2018 Abandoned
Array ( [id] => 16408861 [patent_doc_number] => 10817414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Apparatuses and methods for memory device as a store for block program instructions [patent_app_type] => utility [patent_app_number] => 16/224498 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11262 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/224498
Apparatuses and methods for memory device as a store for block program instructions Dec 17, 2018 Issued
Array ( [id] => 17310006 [patent_doc_number] => 11211131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Adjusting program effective time using program step characteristics [patent_app_type] => utility [patent_app_number] => 16/214373 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7289 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214373
Adjusting program effective time using program step characteristics Dec 9, 2018 Issued
Array ( [id] => 18048174 [patent_doc_number] => 11522132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Storage device and storage unit with a chalcogen element [patent_app_type] => utility [patent_app_number] => 16/962875 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6977 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962875
Storage device and storage unit with a chalcogen element Dec 5, 2018 Issued
Array ( [id] => 16293282 [patent_doc_number] => 10770135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Memory macro which changes operational modes [patent_app_type] => utility [patent_app_number] => 16/205474 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205474
Memory macro which changes operational modes Nov 29, 2018 Issued
Array ( [id] => 14190725 [patent_doc_number] => 20190115068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => DRAM AND METHOD FOR DETERMINING BINARY LOGIC USING A TEST VOLTAGE LEVEL [patent_app_type] => utility [patent_app_number] => 16/201206 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201206
DRAM and method for determining binary logic using a test voltage level Nov 26, 2018 Issued
Array ( [id] => 14109581 [patent_doc_number] => 20190096466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/201329 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201329
Charge extraction from ferroelectric memory cell Nov 26, 2018 Issued
Array ( [id] => 14109583 [patent_doc_number] => 20190096467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => CHARGE EXTRACTION FROM FERROELECTRIC MEMORY CELL [patent_app_type] => utility [patent_app_number] => 16/201351 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201351
Charge extraction from ferroelectric memory cell Nov 26, 2018 Issued
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