Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16249245 [patent_doc_number] => 10748618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Local X-decoder and related memory system with a voltage clamping transistor [patent_app_type] => utility [patent_app_number] => 16/199249 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2888 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16199249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/199249
Local X-decoder and related memory system with a voltage clamping transistor Nov 25, 2018 Issued
Array ( [id] => 16232465 [patent_doc_number] => 10740013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Non-volatile data-storage device with spare block pools using a block clearing method [patent_app_type] => utility [patent_app_number] => 16/198992 [patent_app_country] => US [patent_app_date] => 2018-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6587 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198992
Non-volatile data-storage device with spare block pools using a block clearing method Nov 22, 2018 Issued
Array ( [id] => 15400711 [patent_doc_number] => 10541015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory [patent_app_type] => utility [patent_app_number] => 16/184688 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 16540 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184688
Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory Nov 7, 2018 Issued
Array ( [id] => 14954735 [patent_doc_number] => 10438644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory [patent_app_type] => utility [patent_app_number] => 16/184719 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 16539 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184719 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184719
Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory Nov 7, 2018 Issued
Array ( [id] => 14413359 [patent_doc_number] => 20190172523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => DUAL RAIL DEVICE WITH POWER DETECTOR [patent_app_type] => utility [patent_app_number] => 16/181889 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181889 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181889
Dual rail device with power detector Nov 5, 2018 Issued
Array ( [id] => 16417622 [patent_doc_number] => 10825522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Method for fabricating low and high/medium voltage transistors on substrate [patent_app_type] => utility [patent_app_number] => 16/173406 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3175 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173406 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/173406
Method for fabricating low and high/medium voltage transistors on substrate Oct 28, 2018 Issued
Array ( [id] => 13963551 [patent_doc_number] => 20190058120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses [patent_app_type] => utility [patent_app_number] => 16/168678 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168678
Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses Oct 22, 2018 Abandoned
Array ( [id] => 16047667 [patent_doc_number] => 10685712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor memory device using program mode sets and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/152061 [patent_app_country] => US [patent_app_date] => 2018-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 13861 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152061
Semiconductor memory device using program mode sets and operating method thereof Oct 3, 2018 Issued
Array ( [id] => 15368167 [patent_doc_number] => 20200019848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network [patent_app_type] => utility [patent_app_number] => 16/150606 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -61 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150606 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/150606
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network Oct 2, 2018 Issued
Array ( [id] => 15687493 [patent_doc_number] => 20200098410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => PERPENDICULAR SPIN INJECTION VIA SPATIAL MODULATION OF SPIN ORBIT COUPLING [patent_app_type] => utility [patent_app_number] => 16/141827 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141827
Perpendicular spin injection via spatial modulation of spin orbit coupling Sep 24, 2018 Issued
Array ( [id] => 15518919 [patent_doc_number] => 10566053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Memory cells programmed via multi-mechanism charge transports [patent_app_type] => utility [patent_app_number] => 16/138687 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 13816 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138687
Memory cells programmed via multi-mechanism charge transports Sep 20, 2018 Issued
Array ( [id] => 15657251 [patent_doc_number] => 20200091156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/133655 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133655 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/133655
TWO TRANSISTOR MEMORY CELL USING STACKED THIN-FILM TRANSISTORS Sep 16, 2018 Abandoned
Array ( [id] => 14903707 [patent_doc_number] => 20190295619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MAGNETIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/132991 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132991 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132991
Magnetic device storing first and second values Sep 16, 2018 Issued
Array ( [id] => 15656411 [patent_doc_number] => 20200090736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => POWER AWARE PROGRAMMABLE NEGATIVE BIT LINE CONTROL [patent_app_type] => utility [patent_app_number] => 16/132003 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132003
POWER AWARE PROGRAMMABLE NEGATIVE BIT LINE CONTROL Sep 13, 2018 Abandoned
Array ( [id] => 15332623 [patent_doc_number] => 20200006641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SPACER STACK FOR MAGNETIC TUNNEL JUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/129088 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129088
Sidewall spacer stack for magnetic tunnel junctions Sep 11, 2018 Issued
Array ( [id] => 14784319 [patent_doc_number] => 20190267057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/119285 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119285
Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code Aug 30, 2018 Issued
Array ( [id] => 14784319 [patent_doc_number] => 20190267057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/119285 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119285
Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code Aug 30, 2018 Issued
Array ( [id] => 14784319 [patent_doc_number] => 20190267057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/119285 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119285
Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code Aug 30, 2018 Issued
Array ( [id] => 14784319 [patent_doc_number] => 20190267057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/119285 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119285
Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code Aug 30, 2018 Issued
Array ( [id] => 15759903 [patent_doc_number] => 10622078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => System controller and method for determining the location of the most current data file stored on a plurality of memory circuits [patent_app_type] => utility [patent_app_number] => 16/107306 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 32382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107306
System controller and method for determining the location of the most current data file stored on a plurality of memory circuits Aug 20, 2018 Issued
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