Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15759903 [patent_doc_number] => 10622078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => System controller and method for determining the location of the most current data file stored on a plurality of memory circuits [patent_app_type] => utility [patent_app_number] => 16/107306 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 32382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107306
System controller and method for determining the location of the most current data file stored on a plurality of memory circuits Aug 20, 2018 Issued
Array ( [id] => 14601675 [patent_doc_number] => 10354030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information [patent_app_type] => utility [patent_app_number] => 16/105571 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7814 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105571 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105571
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information Aug 19, 2018 Issued
Array ( [id] => 13581457 [patent_doc_number] => 20180342277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 16/052552 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052552 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052552
Apparatus for low power write and read operations for resistive memory Jul 31, 2018 Issued
Array ( [id] => 14842591 [patent_doc_number] => 20190279696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/049424 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049424
Semiconductor devices configured to store bank addresses and generate bank group addresses Jul 29, 2018 Issued
Array ( [id] => 13908729 [patent_doc_number] => 20190043569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => THREE DIMENSIONAL MEMORY AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/048364 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048364 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048364
Three dimensional NOR flash memory with isolated source lines and method of operating the same Jul 29, 2018 Issued
Array ( [id] => 15822599 [patent_doc_number] => 10636493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Relaxed erase parameters for block erasures in non-volatile storage media [patent_app_type] => utility [patent_app_number] => 16/020742 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020742
Relaxed erase parameters for block erasures in non-volatile storage media Jun 26, 2018 Issued
Array ( [id] => 14238351 [patent_doc_number] => 20190131348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING A LINE-TYPE SELECTION INTERCONNECTION, AND AN ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/020856 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020856
SEMICONDUCTOR MEMORY DEVICE INCLUDING A LINE-TYPE SELECTION INTERCONNECTION, AND AN ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE Jun 26, 2018 Abandoned
Array ( [id] => 15299481 [patent_doc_number] => 20190392876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MEMORY CELL DISTANCE TRACKING CIRCUITS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/018892 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018892
Memory cell distance tracking circuits and methods Jun 25, 2018 Issued
Array ( [id] => 16201711 [patent_doc_number] => 10726886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Memory circuits precharging memory cell arrays and memory devices including the same [patent_app_type] => utility [patent_app_number] => 16/011662 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011662
Memory circuits precharging memory cell arrays and memory devices including the same Jun 18, 2018 Issued
Array ( [id] => 14886691 [patent_doc_number] => 10423386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-24 [patent_title] => FIFO circuit for DDR memory system [patent_app_type] => utility [patent_app_number] => 16/012392 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7160 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012392 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/012392
FIFO circuit for DDR memory system Jun 18, 2018 Issued
Array ( [id] => 15273881 [patent_doc_number] => 20190385675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => METHOD, SYSTEM AND DEVICE FOR MEMORY DEVICE OPERATION [patent_app_type] => utility [patent_app_number] => 16/010253 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/010253
Method, system and device for non-volatile memory device operation Jun 14, 2018 Issued
Array ( [id] => 13579735 [patent_doc_number] => 20180341416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => MEMORY DEVICE WITH DYNAMIC PROGRAM-VERIFY VOLTAGE CALIBRATION [patent_app_type] => utility [patent_app_number] => 16/009091 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009091 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009091
Memory device with dynamic program-verify voltage calibration Jun 13, 2018 Issued
Array ( [id] => 13405081 [patent_doc_number] => 20180254083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => Resistive Memory Apparatus Using Variable-Resistance Channels With High- And Low-Resistance Regions [patent_app_type] => utility [patent_app_number] => 15/970989 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/970989
Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions May 3, 2018 Issued
Array ( [id] => 14800661 [patent_doc_number] => 10403338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Low power memory device with column and row line switches for specific memory cells [patent_app_type] => utility [patent_app_number] => 15/950183 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6038 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950183
Low power memory device with column and row line switches for specific memory cells Apr 10, 2018 Issued
Array ( [id] => 13363293 [patent_doc_number] => 20180233186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => LOW POWER MEMORY DEVICE WITH COLUMN AND ROW LINE SWITCHES FOR SPECIFIC MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 15/949077 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949077 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949077
Low power memory device with column and row line switches for specific memory cells Apr 9, 2018 Issued
Array ( [id] => 16880906 [patent_doc_number] => 11031062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Magnetic memory device and method for controlling a write pulse [patent_app_type] => utility [patent_app_number] => 16/603343 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 8361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603343
Magnetic memory device and method for controlling a write pulse Apr 3, 2018 Issued
Array ( [id] => 15427383 [patent_doc_number] => 10546626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Method and circuit enabling ferroelectric memory to be fixed to a stable state [patent_app_type] => utility [patent_app_number] => 15/944666 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3797 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944666
Method and circuit enabling ferroelectric memory to be fixed to a stable state Apr 2, 2018 Issued
Array ( [id] => 14737889 [patent_doc_number] => 10388353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-20 [patent_title] => Canceling memory cell variations by isolating digit lines [patent_app_type] => utility [patent_app_number] => 15/923700 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16324 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923700
Canceling memory cell variations by isolating digit lines Mar 15, 2018 Issued
Array ( [id] => 15286069 [patent_doc_number] => 10515703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Semiconductor memory device sense amplifier conductor layout and semiconductor memory device using a second read voltage during a read operation [patent_app_type] => utility [patent_app_number] => 15/911383 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 32382 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911383
Semiconductor memory device sense amplifier conductor layout and semiconductor memory device using a second read voltage during a read operation Mar 4, 2018 Issued
Array ( [id] => 13570769 [patent_doc_number] => 20180336932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/909987 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/909987
SEMICONDUCTOR DEVICE Feb 28, 2018 Abandoned
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