Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12631026 [patent_doc_number] => 20180102172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/603563 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603563
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE May 23, 2017 Abandoned
Array ( [id] => 14300409 [patent_doc_number] => 10290335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor device with current path control unit for decreasing the level of a voltage [patent_app_type] => utility [patent_app_number] => 15/493803 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5762 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493803
Semiconductor device with current path control unit for decreasing the level of a voltage Apr 20, 2017 Issued
Array ( [id] => 13098639 [patent_doc_number] => 10068662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Semiconductor device including a roll call circuit for outputting addresses of defective memory cells [patent_app_type] => utility [patent_app_number] => 15/492686 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5207 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492686
Semiconductor device including a roll call circuit for outputting addresses of defective memory cells Apr 19, 2017 Issued
Array ( [id] => 15014735 [patent_doc_number] => 10453523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Magnetic wall utilization-analog memory element and magnetic wall utilization analog memory [patent_app_type] => utility [patent_app_number] => 16/060042 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9967 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16060042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/060042
Magnetic wall utilization-analog memory element and magnetic wall utilization analog memory Apr 13, 2017 Issued
Array ( [id] => 11959156 [patent_doc_number] => 20170263309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => '10-Transistor Non-Volatile Static Random-Access Memory Using A Single Non-Volatile Memory Element And Method Of Operation Thereof' [patent_app_type] => utility [patent_app_number] => 15/487071 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5722 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487071
10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof Apr 12, 2017 Issued
Array ( [id] => 11823910 [patent_doc_number] => 20170212848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'Method for Reduced Load Memory Module' [patent_app_type] => utility [patent_app_number] => 15/481288 [patent_app_country] => US [patent_app_date] => 2017-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481288 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481288
Method for reduced load memory module Apr 5, 2017 Issued
Array ( [id] => 13666601 [patent_doc_number] => 10163471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Time tracking with trits [patent_app_type] => utility [patent_app_number] => 15/474659 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15034 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474659
Time tracking with trits Mar 29, 2017 Issued
Array ( [id] => 13256703 [patent_doc_number] => 10141045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Dual rail device with power detector for controlling power to first and second power domains [patent_app_type] => utility [patent_app_number] => 15/471937 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471937
Dual rail device with power detector for controlling power to first and second power domains Mar 27, 2017 Issued
Array ( [id] => 14737941 [patent_doc_number] => 10388379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Apparatuses and methods for automated dynamic word line start voltage [patent_app_type] => utility [patent_app_number] => 15/531283 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 11037 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15531283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/531283
Apparatuses and methods for automated dynamic word line start voltage Mar 20, 2017 Issued
Array ( [id] => 15547157 [patent_doc_number] => 10573368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Memory system having combined high density, low bandwidth and low density, high bandwidth memories [patent_app_type] => utility [patent_app_number] => 16/098916 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5164 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16098916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/098916
Memory system having combined high density, low bandwidth and low density, high bandwidth memories Mar 5, 2017 Issued
Array ( [id] => 14093607 [patent_doc_number] => 10242716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Semiconductor device having a slit for aligning a connector and a hole for determining positional accuracy of the slit [patent_app_type] => utility [patent_app_number] => 15/448520 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6126 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15448520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/448520
Semiconductor device having a slit for aligning a connector and a hole for determining positional accuracy of the slit Mar 1, 2017 Issued
Array ( [id] => 12334170 [patent_doc_number] => 09947390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Structure and methods of operating two identical 4T random access memories storing the same data [patent_app_type] => utility [patent_app_number] => 15/446807 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 10406 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15446807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/446807
Structure and methods of operating two identical 4T random access memories storing the same data Feb 28, 2017 Issued
Array ( [id] => 11673548 [patent_doc_number] => 20170162271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'REFRESH METHOD FOR FLASH MEMORY AND RELATED MEMORY CONTROLLER THEREOF' [patent_app_type] => utility [patent_app_number] => 15/439916 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4895 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439916 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439916
REFRESH METHOD FOR FLASH MEMORY AND RELATED MEMORY CONTROLLER THEREOF Feb 21, 2017 Abandoned
Array ( [id] => 11981800 [patent_doc_number] => 20170285954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/436921 [patent_app_country] => US [patent_app_date] => 2017-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7234 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436921
Data storage using SLC and TLC memory banks and data maintenance method thereof Feb 19, 2017 Issued
Array ( [id] => 13948279 [patent_doc_number] => 10209914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => System and method for dynamic folding or direct write based on block health in a non-volatile memory system [patent_app_type] => utility [patent_app_number] => 15/420894 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11021 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420894 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420894
System and method for dynamic folding or direct write based on block health in a non-volatile memory system Jan 30, 2017 Issued
Array ( [id] => 14827427 [patent_doc_number] => 10410724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Erase page indicator [patent_app_type] => utility [patent_app_number] => 15/421112 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7252 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421112
Erase page indicator Jan 30, 2017 Issued
Array ( [id] => 13318217 [patent_doc_number] => 20180210646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => EXTENDING SHELF LIFE OF NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 15/411136 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411136 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411136
Extending shelf life of non-volatile memory devices Jan 19, 2017 Issued
Array ( [id] => 13306961 [patent_doc_number] => 20180205017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => INTEGRATION OF CONFINED PHASE CHANGE MEMORY WITH THRESHOLD SWITCHING MATERIAL [patent_app_type] => utility [patent_app_number] => 15/408392 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408392
Integration of confined phase change memory with threshold switching material Jan 16, 2017 Issued
Array ( [id] => 12195334 [patent_doc_number] => 09899067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Efficient calibration of a data eye for memory devices' [patent_app_type] => utility [patent_app_number] => 15/406655 [patent_app_country] => US [patent_app_date] => 2017-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5204 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15406655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/406655
Efficient calibration of a data eye for memory devices Jan 12, 2017 Issued
Array ( [id] => 13692985 [patent_doc_number] => 20170357447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => MEMORY SYSTEM AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/404332 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404332
Memory system for accessing memory dies during program operations and operation method thereof Jan 11, 2017 Issued
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