Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11607790 [patent_doc_number] => 20170125093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'NONVOLATILE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/402565 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10992 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402565
NONVOLATILE MEMORY APPARATUS Jan 9, 2017 Abandoned
Array ( [id] => 11607791 [patent_doc_number] => 20170125094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'NONVOLATILE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/402984 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10994 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402984
NONVOLATILE MEMORY APPARATUS Jan 9, 2017 Abandoned
Array ( [id] => 11652609 [patent_doc_number] => 20170148510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'UPDATING READ VOLTAGES' [patent_app_type] => utility [patent_app_number] => 15/396495 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 24681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396495
UPDATING READ VOLTAGES Dec 30, 2016 Abandoned
Array ( [id] => 11732603 [patent_doc_number] => 20170194045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/389539 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389539 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389539
Semiconductor memory devices with banks with different numbers of memory cells coupled to their bit-lines and memory systems including the same Dec 22, 2016 Issued
Array ( [id] => 12822811 [patent_doc_number] => 20180166109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/378199 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378199 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378199
Memory control device for repeating data during a preamble signal or a postamble signal and memory control method Dec 13, 2016 Issued
Array ( [id] => 12534306 [patent_doc_number] => 10008292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Memory auto repairing circuit preventing transmission of an enable signal and associated method [patent_app_type] => utility [patent_app_number] => 15/378073 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378073 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378073
Memory auto repairing circuit preventing transmission of an enable signal and associated method Dec 13, 2016 Issued
Array ( [id] => 12375108 [patent_doc_number] => 09959928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-01 [patent_title] => Iterative method and apparatus to program a programmable resistance memory element using stabilizing pulses [patent_app_type] => utility [patent_app_number] => 15/377071 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/377071
Iterative method and apparatus to program a programmable resistance memory element using stabilizing pulses Dec 12, 2016 Issued
Array ( [id] => 11665962 [patent_doc_number] => 20170154681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'MEMORY CONTROL METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/366505 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366505
Memory control method and apparatus for programming and erasing areas Nov 30, 2016 Issued
Array ( [id] => 11666326 [patent_doc_number] => 20170155045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses' [patent_app_type] => utility [patent_app_number] => 15/365445 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365445
Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses Nov 29, 2016 Abandoned
Array ( [id] => 12738253 [patent_doc_number] => 20180137918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => METHOD FOR OPERATING MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/350157 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/350157
METHOD FOR OPERATING MEMORY ARRAY Nov 13, 2016 Abandoned
Array ( [id] => 14300453 [patent_doc_number] => 10290357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor memory device and operation method thereof for suppressing floating gate (FG) coupling [patent_app_type] => utility [patent_app_number] => 15/350125 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6403 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350125 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/350125
Semiconductor memory device and operation method thereof for suppressing floating gate (FG) coupling Nov 13, 2016 Issued
Array ( [id] => 13769049 [patent_doc_number] => 10176871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => NAND flash memory comprising a current sensing page buffer preventing voltage from discharging from a node during operation [patent_app_type] => utility [patent_app_number] => 15/349407 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8852 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349407 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/349407
NAND flash memory comprising a current sensing page buffer preventing voltage from discharging from a node during operation Nov 10, 2016 Issued
Array ( [id] => 12713182 [patent_doc_number] => 20180129560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => MEMORY DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/345050 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/345050
Memory device transferring data between master and slave device and semiconductor package including the same Nov 6, 2016 Issued
Array ( [id] => 13434685 [patent_doc_number] => 20180268885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/762752 [patent_app_country] => US [patent_app_date] => 2016-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15762752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/762752
Array of programmable memory elements with an array of second circuit elements Oct 13, 2016 Issued
Array ( [id] => 12595119 [patent_doc_number] => 20180090203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Resistive Memory Apparatus [patent_app_type] => utility [patent_app_number] => 15/278603 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278603
Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions Sep 27, 2016 Issued
Array ( [id] => 15732891 [patent_doc_number] => 10614878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => High speed SRAM device with cross coupled bit line charging circuit and voltage [patent_app_type] => utility [patent_app_number] => 15/273745 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 8364 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273745
High speed SRAM device with cross coupled bit line charging circuit and voltage Sep 22, 2016 Issued
Array ( [id] => 16645665 [patent_doc_number] => 10923533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Semiconductor device having a volatile element and a plurality of non-volatile elements [patent_app_type] => utility [patent_app_number] => 15/763178 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 43 [patent_no_of_words] => 31811 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15763178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/763178
Semiconductor device having a volatile element and a plurality of non-volatile elements Sep 15, 2016 Issued
Array ( [id] => 13681931 [patent_doc_number] => 20160379702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INCREASING LIFETIME OF FERROELECTRIC DEVICES [patent_app_type] => utility [patent_app_number] => 15/263328 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/263328
INCREASING LIFETIME OF FERROELECTRIC DEVICES Sep 11, 2016 Abandoned
Array ( [id] => 12221599 [patent_doc_number] => 20180059958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'HYBRID MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/252886 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16564 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252886
Hybrid memory device using different types of capacitors Aug 30, 2016 Issued
Array ( [id] => 11532394 [patent_doc_number] => 20170092371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'CAPACITIVE-COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRINGS IN THREE DIMENSIONAL ARRAYS' [patent_app_type] => utility [patent_app_number] => 15/248420 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 35044 [patent_no_of_claims] => 280 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248420 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248420
Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays Aug 25, 2016 Issued
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