
Jerome Larry Leboeuf
Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 617 |
| Issued Applications | 492 |
| Pending Applications | 62 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_doc_number] => 09728263
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[patent_title] => 'Method and device for iteratively updating read voltages'
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Array
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[patent_title] => 'STORAGE UNIT AND DRIVING METHOD'
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Array
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[patent_title] => 'Method and device for reducing coupling noise during read operation'
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[patent_title] => 'APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/946841 | Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information | Jul 18, 2013 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/930251 | NAND flash word line management using multiple fragment pools | Jun 27, 2013 | Issued |
Array
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[patent_title] => Apparatus for low power write and read operations for resistive memory
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Array
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[patent_title] => 'SPARE MEMORY EXTERNAL TO PROTECTED MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/926155 | Spare memory external to protected memory | Jun 24, 2013 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921305 | NONVOLATILE MEMORY APPARATUS | Jun 18, 2013 | Abandoned |
Array
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[id] => 10966073
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918681 | Generating stabilized output signals during fuse read operations | Jun 13, 2013 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/909187 | Current sensing amplifier and sensing method thereof | Jun 3, 2013 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/902591 | Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods | May 23, 2013 | Issued |
Array
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