Search

Jerome Larry Leboeuf

Examiner (ID: 3880, Phone: (571)272-7612 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
617
Issued Applications
492
Pending Applications
62
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11831515 [patent_doc_number] => 09728263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Method and device for iteratively updating read voltages' [patent_app_type] => utility [patent_app_number] => 13/967145 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9834 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967145 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967145
Method and device for iteratively updating read voltages Aug 13, 2013 Issued
Array ( [id] => 10158363 [patent_doc_number] => 09190146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Variable resistance memory system with redundancy lines and shielded bit lines' [patent_app_type] => utility [patent_app_number] => 13/962471 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 51 [patent_no_of_words] => 24705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 443 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13962471 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/962471
Variable resistance memory system with redundancy lines and shielded bit lines Aug 7, 2013 Issued
Array ( [id] => 9317673 [patent_doc_number] => 20140050011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'STORAGE UNIT AND DRIVING METHOD' [patent_app_type] => utility [patent_app_number] => 13/960519 [patent_app_country] => US [patent_app_date] => 2013-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7745 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960519 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/960519
Ionic storage unit and driving method Aug 5, 2013 Issued
Array ( [id] => 10099690 [patent_doc_number] => 09136006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Method and device for reducing coupling noise during read operation' [patent_app_type] => utility [patent_app_number] => 13/946123 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946123
Method and device for reducing coupling noise during read operation Jul 18, 2013 Issued
Array ( [id] => 9811159 [patent_doc_number] => 20150023104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'APPARATUSES AND METHODS FOR MEASURING AN ELECTRICAL CHARACTERISTIC OF A MODEL SIGNAL LINE AND PROVIDING MEASUREMENT INFORMATION' [patent_app_type] => utility [patent_app_number] => 13/946841 [patent_app_country] => US [patent_app_date] => 2013-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7903 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13946841 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/946841
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information Jul 18, 2013 Issued
Array ( [id] => 10138274 [patent_doc_number] => 09171595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Semiconductor device including negative bias voltage generation circuit' [patent_app_type] => utility [patent_app_number] => 13/935815 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11631 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935815
Semiconductor device including negative bias voltage generation circuit Jul 4, 2013 Issued
Array ( [id] => 11227322 [patent_doc_number] => 09455048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'NAND flash word line management using multiple fragment pools' [patent_app_type] => utility [patent_app_number] => 13/930251 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13930251 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/930251
NAND flash word line management using multiple fragment pools Jun 27, 2013 Issued
Array ( [id] => 13098571 [patent_doc_number] => 10068628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Apparatus for low power write and read operations for resistive memory [patent_app_type] => utility [patent_app_number] => 14/129277 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10826 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14129277 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/129277
Apparatus for low power write and read operations for resistive memory Jun 27, 2013 Issued
Array ( [id] => 10973286 [patent_doc_number] => 20140376320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-25 [patent_title] => 'SPARE MEMORY EXTERNAL TO PROTECTED MEMORY' [patent_app_type] => utility [patent_app_number] => 13/926155 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926155 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/926155
Spare memory external to protected memory Jun 24, 2013 Issued
Array ( [id] => 9559608 [patent_doc_number] => 20140177319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'NONVOLATILE MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/921305 [patent_app_country] => US [patent_app_date] => 2013-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10973 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/921305
NONVOLATILE MEMORY APPARATUS Jun 18, 2013 Abandoned
Array ( [id] => 10966073 [patent_doc_number] => 20140369105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'GENERATING OUTPUT SIGNAL DURING READ OPERATION' [patent_app_type] => utility [patent_app_number] => 13/918681 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4171 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918681 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/918681
Generating stabilized output signals during fuse read operations Jun 13, 2013 Issued
Array ( [id] => 10059828 [patent_doc_number] => 09099191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Current sensing amplifier and sensing method thereof' [patent_app_type] => utility [patent_app_number] => 13/909187 [patent_app_country] => US [patent_app_date] => 2013-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 12154 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909187 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/909187
Current sensing amplifier and sensing method thereof Jun 3, 2013 Issued
Array ( [id] => 10151615 [patent_doc_number] => 09183910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Semiconductor memory devices for alternately selecting bit lines' [patent_app_type] => utility [patent_app_number] => 13/907223 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 78 [patent_no_of_words] => 25332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13907223 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/907223
Semiconductor memory devices for alternately selecting bit lines May 30, 2013 Issued
Array ( [id] => 10944925 [patent_doc_number] => 20140347945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'APPARATUSES INCLUDING A MEMORY ARRAY WITH SEPARATE GLOBAL READ AND WRITE LINES AND/OR SENSE AMPLIFIER REGION COLUMN SELECT LINE AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 13/902591 [patent_app_country] => US [patent_app_date] => 2013-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5645 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13902591 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/902591
Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods May 23, 2013 Issued
Array ( [id] => 11253635 [patent_doc_number] => 09479152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Semiconductor device and method for driving semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/894783 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 13374 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894783
Semiconductor device and method for driving semiconductor device May 14, 2013 Issued
Array ( [id] => 10925111 [patent_doc_number] => 20140328132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'MEMORY MARGIN MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/886971 [patent_app_country] => US [patent_app_date] => 2013-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886971 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/886971
Memory margin management May 2, 2013 Issued
Array ( [id] => 10073261 [patent_doc_number] => 09111622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Self referencing sense amplifier for spin torque MRAM' [patent_app_type] => utility [patent_app_number] => 13/872993 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872993 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872993
Self referencing sense amplifier for spin torque MRAM Apr 28, 2013 Issued
Array ( [id] => 11831503 [patent_doc_number] => 09728251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Resistance variable memory sensing using programming signals' [patent_app_type] => utility [patent_app_number] => 13/869571 [patent_app_country] => US [patent_app_date] => 2013-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7101 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869571 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/869571
Resistance variable memory sensing using programming signals Apr 23, 2013 Issued
Array ( [id] => 11802101 [patent_doc_number] => 09542992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'SRAM core cell design with write assist' [patent_app_type] => utility [patent_app_number] => 13/865281 [patent_app_country] => US [patent_app_date] => 2013-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13865281 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/865281
SRAM core cell design with write assist Apr 17, 2013 Issued
Array ( [id] => 9979070 [patent_doc_number] => 09025393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Method of optimizing solid state drive soft retry voltages' [patent_app_type] => utility [patent_app_number] => 13/856179 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856179 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856179
Method of optimizing solid state drive soft retry voltages Apr 2, 2013 Issued
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