Jerome Larry Leboeuf

Array ( [id] => 19610165 [patent_doc_number] => 12159040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/899974 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 35455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18097038 [patent_doc_number] => 20220415379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories [patent_app_type] => utility [patent_app_number] => 17/895433 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18990860 [patent_doc_number] => 20240062829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/888781 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18038871 [patent_doc_number] => 20220383087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => COMPENSATION FOR REFERENCE TRANSISTORS AND MEMORY CELLS IN ANALOG NEURO MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/885437 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18060596 [patent_doc_number] => 20220391682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network [patent_app_type] => utility [patent_app_number] => 17/885431 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18308949 [patent_doc_number] => 20230112849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MEMORY DEVICE AND METHOD FOR DETERMINING START POINT AND END POINT OF VERIFICATION OPERATION OF TARGET STATE DURING PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/881009 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20162953 [patent_doc_number] => 12389610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Memory device with memory strings using variable resistance memory regions [patent_app_type] => utility [patent_app_number] => 17/877714 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 78 [patent_no_of_words] => 13685 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19093699 [patent_doc_number] => 11955163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Method and circuit for adaptive column-select line signal generation [patent_app_type] => utility [patent_app_number] => 17/875449 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 8030 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18943158 [patent_doc_number] => 20240038297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Buried Metal Techniques [patent_app_type] => utility [patent_app_number] => 17/874611 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18941457 [patent_doc_number] => 20240036596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => VOLTAGE REGULATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/874867 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18985520 [patent_doc_number] => 11910733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Generating self-aligned heater for PCRAM using filaments [patent_app_type] => utility [patent_app_number] => 17/813802 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20776508 [patent_doc_number] => 12660200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Memory cells with lever electrodes and arrangements thereof [patent_app_type] => utility [patent_app_number] => 17/813807 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18633606 [patent_doc_number] => 20230292533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => NEURAL NETWORK SYSTEM, HIGH EFFICIENCY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/813599 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17985730 [patent_doc_number] => 20220351767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/864970 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18224406 [patent_doc_number] => 20230063400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => LOW_POWERED MEMORY DEVICE AND METHOD OF CONTROLLING POWER OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/865381 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18900586 [patent_doc_number] => 20240016071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => Multi-Bit Storage Device Using Phase Change Material [patent_app_type] => utility [patent_app_number] => 17/810688 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18158267 [patent_doc_number] => 20230024858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => PROCESSING APPARATUSES INCLUDING MAGNETIC RESISTORS [patent_app_type] => utility [patent_app_number] => 17/834074 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17869110 [patent_doc_number] => 20220291847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => MEMORY DEVICE WITH DYNAMIC PROGRAM-VERIFY VOLTAGE CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/826733 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19742894 [patent_doc_number] => 12219756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof [patent_app_type] => utility [patent_app_number] => 17/664550 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 77 [patent_no_of_words] => 30295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17855569 [patent_doc_number] => 20220285612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/750484 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750484 [rel_patent_id] =>[rel_patent_doc_number] =>)