Jerry D. Robbins

Array ( [id] => 2859472 [patent_doc_number] => 05105389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/621643 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/105/05105389.pdf [firstpage_image] =>[orig_patent_app_number] => 621643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3098512 [patent_doc_number] => 05285527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Predictive historical cache memory' [patent_app_type] => 1 [patent_app_number] => 7/619588 [patent_app_country] => US [patent_app_date] => 1990-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3879 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285527.pdf [firstpage_image] =>[orig_patent_app_number] => 619588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2905032 [patent_doc_number] => 05210845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Controller for two-way set associative cache' [patent_app_type] => 1 [patent_app_number] => 7/618708 [patent_app_country] => US [patent_app_date] => 1990-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 8919 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 561 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210845.pdf [firstpage_image] =>[orig_patent_app_number] => 618708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2988570 [patent_doc_number] => 05226138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Method for selectively transferring data instructions to a cache memory' [patent_app_type] => 1 [patent_app_number] => 7/618698 [patent_app_country] => US [patent_app_date] => 1990-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2376 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/226/05226138.pdf [firstpage_image] =>[orig_patent_app_number] => 618698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2915654 [patent_doc_number] => 05249282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Integrated cache memory system with primary and secondary cache memories' [patent_app_type] => 1 [patent_app_number] => 7/616427 [patent_app_country] => US [patent_app_date] => 1990-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7286 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249282.pdf [firstpage_image] =>[orig_patent_app_number] => 616427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2757920 [patent_doc_number] => 05038324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'Separation circuit for a DRAM' [patent_app_type] => 1 [patent_app_number] => 7/616225 [patent_app_country] => US [patent_app_date] => 1990-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3706 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/038/05038324.pdf [firstpage_image] =>[orig_patent_app_number] => 616225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799420 [patent_doc_number] => 05155835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Multilevel, hierarchical, dynamically mapped data storage subsystem' [patent_app_type] => 1 [patent_app_number] => 7/615329 [patent_app_country] => US [patent_app_date] => 1990-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11483 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155835.pdf [firstpage_image] =>[orig_patent_app_number] => 615329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2849574 [patent_doc_number] => 05161218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Memory controller for using reserved DRAM addresses for EMS' [patent_app_type] => 1 [patent_app_number] => 7/614183 [patent_app_country] => US [patent_app_date] => 1990-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1937 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/161/05161218.pdf [firstpage_image] =>[orig_patent_app_number] => 614183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2901835 [patent_doc_number] => 05239639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Efficient memory controller with an independent clock' [patent_app_type] => 1 [patent_app_number] => 7/611183 [patent_app_country] => US [patent_app_date] => 1990-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4524 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239639.pdf [firstpage_image] =>[orig_patent_app_number] => 611183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2887797 [patent_doc_number] => 05159573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Apparatus for controlling outputs of read data in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/610885 [patent_app_country] => US [patent_app_date] => 1990-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2452 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159573.pdf [firstpage_image] =>[orig_patent_app_number] => 610885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840493 [patent_doc_number] => 05175704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/607468 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 5259 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175704.pdf [firstpage_image] =>[orig_patent_app_number] => 607468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2843898 [patent_doc_number] => 05129075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Data processor with on-chip logical addressing and off-chip physical addressing' [patent_app_type] => 1 [patent_app_number] => 7/596751 [patent_app_country] => US [patent_app_date] => 1990-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8276 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129075.pdf [firstpage_image] =>[orig_patent_app_number] => 596751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2915630 [patent_doc_number] => 05249281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Testable RAM architecture in a microprocessor having embedded cache memory' [patent_app_type] => 1 [patent_app_number] => 7/596986 [patent_app_country] => US [patent_app_date] => 1990-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5177 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249281.pdf [firstpage_image] =>[orig_patent_app_number] => 596986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2816940 [patent_doc_number] => 05146572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Multiple data format interface' [patent_app_type] => 1 [patent_app_number] => 7/593606 [patent_app_country] => US [patent_app_date] => 1990-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2612 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146572.pdf [firstpage_image] =>[orig_patent_app_number] => 593606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2743448 [patent_doc_number] => 05077688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Semiconductor memory device having improved memory cells provided with cylindrical type capacitors' [patent_app_type] => 1 [patent_app_number] => 7/591635 [patent_app_country] => US [patent_app_date] => 1990-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 6271 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077688.pdf [firstpage_image] =>[orig_patent_app_number] => 591635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2810305 [patent_doc_number] => 05140550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/591883 [patent_app_country] => US [patent_app_date] => 1990-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9324 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140550.pdf [firstpage_image] =>[orig_patent_app_number] => 591883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2930875 [patent_doc_number] => 05206939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'System and method for disk mapping and data retrieval' [patent_app_type] => 1 [patent_app_number] => 7/586796 [patent_app_country] => US [patent_app_date] => 1990-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6883 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206939.pdf [firstpage_image] =>[orig_patent_app_number] => 586796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2679898 [patent_doc_number] => 05047983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Semiconductor storage device with redundancy arrangement' [patent_app_type] => 1 [patent_app_number] => 7/586399 [patent_app_country] => US [patent_app_date] => 1990-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5355 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047983.pdf [firstpage_image] =>[orig_patent_app_number] => 586399 [rel_patent_id] =>[rel_patent_doc_number] =>)