Search

Jerry D. Robbins

Examiner (ID: 17637, Phone: (571)272-7585 , Office: P/2859 )

Most Active Art Unit
2859
Art Unit(s)
2859
Total Applications
825
Issued Applications
594
Pending Applications
71
Abandoned Applications
192

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2857779 [patent_doc_number] => 05107461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'EEPROM memory cell with improved protection against errors due to cell breakdown' [patent_app_type] => 1 [patent_app_number] => 7/549763 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1556 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/107/05107461.pdf [firstpage_image] =>[orig_patent_app_number] => 549763 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549763
EEPROM memory cell with improved protection against errors due to cell breakdown Jul 8, 1990 Issued
Array ( [id] => 2847361 [patent_doc_number] => 05121353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Ferroelectric capacitor memory circuit MOS setting and transmission transistor' [patent_app_type] => 1 [patent_app_number] => 7/548823 [patent_app_country] => US [patent_app_date] => 1990-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3693 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121353.pdf [firstpage_image] =>[orig_patent_app_number] => 548823 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/548823
Ferroelectric capacitor memory circuit MOS setting and transmission transistor Jul 5, 1990 Issued
Array ( [id] => 2703267 [patent_doc_number] => 05020029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Static semiconductor memory device with predetermined threshold voltages' [patent_app_type] => 1 [patent_app_number] => 7/547263 [patent_app_country] => US [patent_app_date] => 1990-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5945 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/020/05020029.pdf [firstpage_image] =>[orig_patent_app_number] => 547263 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/547263
Static semiconductor memory device with predetermined threshold voltages Jul 2, 1990 Issued
07/545781 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREFOR Jun 28, 1990 Abandoned
07/544283 METHOD AND APPARATUS FOR TESTING MEMORIES Jun 24, 1990 Abandoned
Array ( [id] => 2927830 [patent_doc_number] => 05179687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Semiconductor memory device containing a cache and an operation method thereof' [patent_app_type] => 1 [patent_app_number] => 7/542682 [patent_app_country] => US [patent_app_date] => 1990-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 9537 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179687.pdf [firstpage_image] =>[orig_patent_app_number] => 542682 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/542682
Semiconductor memory device containing a cache and an operation method thereof Jun 24, 1990 Issued
Array ( [id] => 2948117 [patent_doc_number] => 05247639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Microprocessor having cache bypass signal terminal' [patent_app_type] => 1 [patent_app_number] => 7/540617 [patent_app_country] => US [patent_app_date] => 1990-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3981 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247639.pdf [firstpage_image] =>[orig_patent_app_number] => 540617 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/540617
Microprocessor having cache bypass signal terminal Jun 19, 1990 Issued
Array ( [id] => 2794514 [patent_doc_number] => 05093805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-03 [patent_title] => 'Non-binary memory array' [patent_app_type] => 1 [patent_app_number] => 7/541122 [patent_app_country] => US [patent_app_date] => 1990-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2877 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/093/05093805.pdf [firstpage_image] =>[orig_patent_app_number] => 541122 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/541122
Non-binary memory array Jun 19, 1990 Issued
Array ( [id] => 2766708 [patent_doc_number] => 05043943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Cache memory with a parity write control circuit' [patent_app_type] => 1 [patent_app_number] => 7/539651 [patent_app_country] => US [patent_app_date] => 1990-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4641 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043943.pdf [firstpage_image] =>[orig_patent_app_number] => 539651 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/539651
Cache memory with a parity write control circuit Jun 17, 1990 Issued
Array ( [id] => 2857918 [patent_doc_number] => 05111386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Cache contained type semiconductor memory device and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 7/538605 [patent_app_country] => US [patent_app_date] => 1990-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 7338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111386.pdf [firstpage_image] =>[orig_patent_app_number] => 538605 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/538605
Cache contained type semiconductor memory device and operating method therefor Jun 13, 1990 Issued
07/536217 METHOD AND APPARATUS FOR A LOAD AND FLAG INSTRUCTION Jun 10, 1990 Abandoned
Array ( [id] => 2796929 [patent_doc_number] => 05155701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Semiconductor integrated circuit device and method of testing the same' [patent_app_type] => 1 [patent_app_number] => 7/535298 [patent_app_country] => US [patent_app_date] => 1990-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7075 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155701.pdf [firstpage_image] =>[orig_patent_app_number] => 535298 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535298
Semiconductor integrated circuit device and method of testing the same Jun 7, 1990 Issued
Array ( [id] => 2813940 [patent_doc_number] => 05115411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Dual port memory system' [patent_app_type] => 1 [patent_app_number] => 7/534081 [patent_app_country] => US [patent_app_date] => 1990-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 3699 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115411.pdf [firstpage_image] =>[orig_patent_app_number] => 534081 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/534081
Dual port memory system Jun 5, 1990 Issued
Array ( [id] => 2951342 [patent_doc_number] => 05261068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Dual path memory retrieval system for an interleaved dynamic RAM memory unit' [patent_app_type] => 1 [patent_app_number] => 7/530137 [patent_app_country] => US [patent_app_date] => 1990-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6781 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/261/05261068.pdf [firstpage_image] =>[orig_patent_app_number] => 530137 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/530137
Dual path memory retrieval system for an interleaved dynamic RAM memory unit May 24, 1990 Issued
Array ( [id] => 2800939 [patent_doc_number] => 05103426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'Decoding circuit and method for functional block selection' [patent_app_type] => 1 [patent_app_number] => 7/528511 [patent_app_country] => US [patent_app_date] => 1990-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5158 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/103/05103426.pdf [firstpage_image] =>[orig_patent_app_number] => 528511 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/528511
Decoding circuit and method for functional block selection May 24, 1990 Issued
Array ( [id] => 2881764 [patent_doc_number] => 05091885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Dynamic type random-access memory having improved timing characteristics' [patent_app_type] => 1 [patent_app_number] => 7/523663 [patent_app_country] => US [patent_app_date] => 1990-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5739 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091885.pdf [firstpage_image] =>[orig_patent_app_number] => 523663 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/523663
Dynamic type random-access memory having improved timing characteristics May 14, 1990 Issued
Array ( [id] => 2679917 [patent_doc_number] => 05047984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Internal synchronous static RAM' [patent_app_type] => 1 [patent_app_number] => 7/520943 [patent_app_country] => US [patent_app_date] => 1990-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3805 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/047/05047984.pdf [firstpage_image] =>[orig_patent_app_number] => 520943 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/520943
Internal synchronous static RAM May 8, 1990 Issued
Array ( [id] => 2655585 [patent_doc_number] => 04980860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry' [patent_app_type] => 1 [patent_app_number] => 7/521000 [patent_app_country] => US [patent_app_date] => 1990-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5573 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980860.pdf [firstpage_image] =>[orig_patent_app_number] => 521000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/521000
Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry May 7, 1990 Issued
07/515341 SEMICONDUCTOR MEMORY Apr 29, 1990 Abandoned
Array ( [id] => 2877870 [patent_doc_number] => 05097450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Semiconductor memory device having a plurality of memory blocks' [patent_app_type] => 1 [patent_app_number] => 7/515336 [patent_app_country] => US [patent_app_date] => 1990-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4419 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097450.pdf [firstpage_image] =>[orig_patent_app_number] => 515336 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/515336
Semiconductor memory device having a plurality of memory blocks Apr 29, 1990 Issued
Menu