Jesse A. Fenty

Array ( [id] => 4297393 [patent_doc_number] => 06236086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'ESD protection with buried diffusion' [patent_app_type] => 1 [patent_app_number] => 9/063103 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3245 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236086.pdf [firstpage_image] =>[orig_patent_app_number] => 063103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4224776 [patent_doc_number] => 06040615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Semiconductor device with moisture resistant fuse portion' [patent_app_type] => 1 [patent_app_number] => 9/059280 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 3204 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040615.pdf [firstpage_image] =>[orig_patent_app_number] => 059280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161684 [patent_doc_number] => 06104077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor device having gate electrode with a sidewall air gap' [patent_app_type] => 1 [patent_app_number] => 9/060160 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3142 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104077.pdf [firstpage_image] =>[orig_patent_app_number] => 060160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161272 [patent_doc_number] => 06107666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'High density ROM and a method of making the same' [patent_app_type] => 1 [patent_app_number] => 9/053023 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 2742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107666.pdf [firstpage_image] =>[orig_patent_app_number] => 053023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3939038 [patent_doc_number] => 05939767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Structure and process for buried diode formation in CMOS' [patent_app_type] => 1 [patent_app_number] => 9/052512 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 10067 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939767.pdf [firstpage_image] =>[orig_patent_app_number] => 052512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197635 [patent_doc_number] => 06043546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Planar channel-type MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/050432 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2699 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043546.pdf [firstpage_image] =>[orig_patent_app_number] => 050432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187071 [patent_doc_number] => 06020614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method of reducing substrate noise coupling in mixed signal integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/047651 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4922 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020614.pdf [firstpage_image] =>[orig_patent_app_number] => 047651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953978 [patent_doc_number] => 05977609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method and apparatus for insulating material using trenches' [patent_app_type] => 1 [patent_app_number] => 9/045819 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977609.pdf [firstpage_image] =>[orig_patent_app_number] => 045819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7647076 [patent_doc_number] => 06476442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Pseudo-Schottky diode' [patent_app_type] => B1 [patent_app_number] => 09/037557 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 50 [patent_no_of_words] => 12891 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476442.pdf [firstpage_image] =>[orig_patent_app_number] => 09037557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239149 [patent_doc_number] => 06075271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Semiconductor device inhibiting parasitic effects during electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 9/033752 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5052 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075271.pdf [firstpage_image] =>[orig_patent_app_number] => 033752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252847 [patent_doc_number] => 06137119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connecting the conductive region to the substrate after manufacture' [patent_app_type] => 1 [patent_app_number] => 9/032181 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3466 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137119.pdf [firstpage_image] =>[orig_patent_app_number] => 032181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4162841 [patent_doc_number] => 06157070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Protection circuit against latch-up in a multiple-supply integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/027533 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3132 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157070.pdf [firstpage_image] =>[orig_patent_app_number] => 027533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950194 [patent_doc_number] => 05990526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Memory device with a cell array in triple well, and related manufacturing process' [patent_app_type] => 1 [patent_app_number] => 9/027343 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3235 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990526.pdf [firstpage_image] =>[orig_patent_app_number] => 027343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7026611 [patent_doc_number] => 20010013615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'INTEGRATED CIRCUIT FABRICATION' [patent_app_type] => new [patent_app_number] => 09/024601 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1769 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013615.pdf [firstpage_image] =>[orig_patent_app_number] => 09024601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422743 [patent_doc_number] => 06194781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/023432 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4686 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194781.pdf [firstpage_image] =>[orig_patent_app_number] => 023432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1497033 [patent_doc_number] => 06404021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Laminated structure and a method of forming the same' [patent_app_type] => B1 [patent_app_number] => 09/023712 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5400 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404021.pdf [firstpage_image] =>[orig_patent_app_number] => 09023712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4111279 [patent_doc_number] => 06023080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Input/output connection structure of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/022123 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3172 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023080.pdf [firstpage_image] =>[orig_patent_app_number] => 022123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253336 [patent_doc_number] => 06137154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Bipolar transistor with increased early voltage' [patent_app_type] => 1 [patent_app_number] => 9/017571 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2894 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137154.pdf [firstpage_image] =>[orig_patent_app_number] => 017571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255139 [patent_doc_number] => 06222273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'System having vias including conductive spacers' [patent_app_type] => 1 [patent_app_number] => 9/016753 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3122 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222273.pdf [firstpage_image] =>[orig_patent_app_number] => 016753 [rel_patent_id] =>[rel_patent_doc_number] =>)