Search

Jessica L. Rossi

Supervisory Patent Examiner (ID: 6887, Phone: (571)272-1223 , Office: P/4100 )

Most Active Art Unit
1733
Art Unit(s)
1791, 4132, 1733, OPT
Total Applications
436
Issued Applications
256
Pending Applications
32
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3691381 [patent_doc_number] => 05633829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Serial access memory device capable of controlling order of access to memory cell areas' [patent_app_type] => 1 [patent_app_number] => 7/739786 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7677 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633829.pdf [firstpage_image] =>[orig_patent_app_number] => 739786 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/739786
Serial access memory device capable of controlling order of access to memory cell areas Jul 30, 1991 Issued
Array ( [id] => 2813394 [patent_doc_number] => 05124945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Method and apparatus for verifying the state of a plurality of electrically programmable memory cells' [patent_app_type] => 1 [patent_app_number] => 7/737830 [patent_app_country] => US [patent_app_date] => 1991-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5883 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124945.pdf [firstpage_image] =>[orig_patent_app_number] => 737830 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/737830
Method and apparatus for verifying the state of a plurality of electrically programmable memory cells Jul 28, 1991 Issued
Array ( [id] => 2928808 [patent_doc_number] => 05206830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-27 [patent_title] => 'Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus' [patent_app_type] => 1 [patent_app_number] => 7/733126 [patent_app_country] => US [patent_app_date] => 1991-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/206/05206830.pdf [firstpage_image] =>[orig_patent_app_number] => 733126 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/733126
Refresh control circuit of pseudo static random access memory and pseudo static random access memory apparatus Jul 18, 1991 Issued
Array ( [id] => 2824196 [patent_doc_number] => 05122988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Data stream smoothing using a FIFO memory' [patent_app_type] => 1 [patent_app_number] => 7/732351 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1752 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122988.pdf [firstpage_image] =>[orig_patent_app_number] => 732351 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/732351
Data stream smoothing using a FIFO memory Jul 16, 1991 Issued
Array ( [id] => 2931640 [patent_doc_number] => 05200919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use' [patent_app_type] => 1 [patent_app_number] => 7/730566 [patent_app_country] => US [patent_app_date] => 1991-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4409 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200919.pdf [firstpage_image] =>[orig_patent_app_number] => 730566 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/730566
Electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use Jul 14, 1991 Issued
Array ( [id] => 2851000 [patent_doc_number] => 05172335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Semiconductor memory with divided bit load and data bus lines' [patent_app_type] => 1 [patent_app_number] => 7/727314 [patent_app_country] => US [patent_app_date] => 1991-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3727 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/172/05172335.pdf [firstpage_image] =>[orig_patent_app_number] => 727314 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/727314
Semiconductor memory with divided bit load and data bus lines Jun 30, 1991 Issued
07/713026 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Jun 6, 1991 Abandoned
Array ( [id] => 2795149 [patent_doc_number] => 05142496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Method for measuring V.sub.T \'s less than zero without applying negative voltages' [patent_app_type] => 1 [patent_app_number] => 7/709525 [patent_app_country] => US [patent_app_date] => 1991-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142496.pdf [firstpage_image] =>[orig_patent_app_number] => 709525 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/709525
Method for measuring V.sub.T 's less than zero without applying negative voltages Jun 2, 1991 Issued
07/709924 STATIC MEMORIES AND METHODS OF READING STATIC MEMORIES May 29, 1991 Abandoned
Array ( [id] => 2881782 [patent_doc_number] => 05091886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Dual current data bus clamp circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/706206 [patent_app_country] => US [patent_app_date] => 1991-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091886.pdf [firstpage_image] =>[orig_patent_app_number] => 706206 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/706206
Dual current data bus clamp circuit of semiconductor memory device May 27, 1991 Issued
07/698546 FLOATING GATE NON-VOLATILE MEMORY WITH DEEP POWER DOWN AND WRITE LOCK-OUT May 9, 1991 Abandoned
07/692802 WORDLINE DRIVER CIRCUIT FOR EEPROM MEMORY CELL Apr 23, 1991 Abandoned
Array ( [id] => 3835979 [patent_doc_number] => 05732015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'SRAM with a programmable reference voltage' [patent_app_type] => 1 [patent_app_number] => 7/690133 [patent_app_country] => US [patent_app_date] => 1991-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6327 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732015.pdf [firstpage_image] =>[orig_patent_app_number] => 690133 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/690133
SRAM with a programmable reference voltage Apr 22, 1991 Issued
Array ( [id] => 2896374 [patent_doc_number] => 05214602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Dynamic memory word line driver scheme' [patent_app_type] => 1 [patent_app_number] => 7/680746 [patent_app_country] => US [patent_app_date] => 1991-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1579 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214602.pdf [firstpage_image] =>[orig_patent_app_number] => 680746 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/680746
Dynamic memory word line driver scheme Apr 4, 1991 Issued
Array ( [id] => 3483618 [patent_doc_number] => 05428574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Static RAM with test features' [patent_app_type] => 1 [patent_app_number] => 7/701536 [patent_app_country] => US [patent_app_date] => 1991-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11930 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428574.pdf [firstpage_image] =>[orig_patent_app_number] => 701536 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/701536
Static RAM with test features Mar 27, 1991 Issued
Array ( [id] => 2817102 [patent_doc_number] => 05157631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-20 [patent_title] => 'Random access memory device with dual charging circuits different in current driving capability' [patent_app_type] => 1 [patent_app_number] => 7/673914 [patent_app_country] => US [patent_app_date] => 1991-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3953 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/157/05157631.pdf [firstpage_image] =>[orig_patent_app_number] => 673914 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/673914
Random access memory device with dual charging circuits different in current driving capability Mar 24, 1991 Issued
Array ( [id] => 2785833 [patent_doc_number] => 05132936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'MOS memory circuit with fast access time' [patent_app_type] => 1 [patent_app_number] => 7/675021 [patent_app_country] => US [patent_app_date] => 1991-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2963 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132936.pdf [firstpage_image] =>[orig_patent_app_number] => 675021 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/675021
MOS memory circuit with fast access time Mar 24, 1991 Issued
Array ( [id] => 3076521 [patent_doc_number] => 05311468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Random access memory with a serial register arranged for quick access of a second bit from an arbitrary address' [patent_app_type] => 1 [patent_app_number] => 7/672806 [patent_app_country] => US [patent_app_date] => 1991-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5275 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311468.pdf [firstpage_image] =>[orig_patent_app_number] => 672806 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/672806
Random access memory with a serial register arranged for quick access of a second bit from an arbitrary address Mar 20, 1991 Issued
Array ( [id] => 2800921 [patent_doc_number] => 05103425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'Zener regulated programming circuit for a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 7/666964 [patent_app_country] => US [patent_app_date] => 1991-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3516 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/103/05103425.pdf [firstpage_image] =>[orig_patent_app_number] => 666964 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/666964
Zener regulated programming circuit for a nonvolatile memory Mar 10, 1991 Issued
Array ( [id] => 2815574 [patent_doc_number] => 05148397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Semiconductor memory with externally controlled dummy comparator' [patent_app_type] => 1 [patent_app_number] => 7/664404 [patent_app_country] => US [patent_app_date] => 1991-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3006 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/148/05148397.pdf [firstpage_image] =>[orig_patent_app_number] => 664404 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/664404
Semiconductor memory with externally controlled dummy comparator Mar 3, 1991 Issued
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