| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2664540
[patent_doc_number] => 04962478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-09
[patent_title] => 'High speed programmable read only memory device having a high integration density and diode in the programming path'
[patent_app_type] => 1
[patent_app_number] => 7/421876
[patent_app_country] => US
[patent_app_date] => 1989-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4862
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 443
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/962/04962478.pdf
[firstpage_image] =>[orig_patent_app_number] => 421876
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/421876 | High speed programmable read only memory device having a high integration density and diode in the programming path | Oct 12, 1989 | Issued |
Array
(
[id] => 2719464
[patent_doc_number] => 05018100
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/420016
[patent_app_country] => US
[patent_app_date] => 1989-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8573
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/018/05018100.pdf
[firstpage_image] =>[orig_patent_app_number] => 420016
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/420016 | Semiconductor memory device | Oct 10, 1989 | Issued |
Array
(
[id] => 2776402
[patent_doc_number] => 05036490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Memory device with dual cantilever means'
[patent_app_type] => 1
[patent_app_number] => 7/414128
[patent_app_country] => US
[patent_app_date] => 1989-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 4205
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/036/05036490.pdf
[firstpage_image] =>[orig_patent_app_number] => 414128
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/414128 | Memory device with dual cantilever means | Sep 27, 1989 | Issued |
Array
(
[id] => 2889134
[patent_doc_number] => 05119336
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-02
[patent_title] => 'Memory write protection circuit'
[patent_app_type] => 1
[patent_app_number] => 7/412507
[patent_app_country] => US
[patent_app_date] => 1989-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 3772
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 586
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/119/05119336.pdf
[firstpage_image] =>[orig_patent_app_number] => 412507
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/412507 | Memory write protection circuit | Sep 25, 1989 | Issued |
Array
(
[id] => 2731509
[patent_doc_number] => 05025415
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-18
[patent_title] => 'Memory card'
[patent_app_type] => 1
[patent_app_number] => 7/412077
[patent_app_country] => US
[patent_app_date] => 1989-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 3689
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/025/05025415.pdf
[firstpage_image] =>[orig_patent_app_number] => 412077
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/412077 | Memory card | Sep 24, 1989 | Issued |
| 07/411927 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH NAND TYPE MEMORY CELL ARRAYS | Sep 24, 1989 | Abandoned |
| 07/411087 | MEMORY WITH SELECTIVE ADDRESS TRANSITION DETECTION FOR CACHE OPERATION | Sep 21, 1989 | Abandoned |
| 07/410767 | DATA STREAM SMOOTHING USING A FIFO MEMORY | Sep 20, 1989 | Abandoned |
Array
(
[id] => 2640463
[patent_doc_number] => 04958319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-18
[patent_title] => 'Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs'
[patent_app_type] => 1
[patent_app_number] => 7/409578
[patent_app_country] => US
[patent_app_date] => 1989-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1939
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/958/04958319.pdf
[firstpage_image] =>[orig_patent_app_number] => 409578
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/409578 | Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs | Sep 18, 1989 | Issued |
| 07/409307 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE FOR CONTROLLING THE POTENTIALS ON BIT LINES | Sep 18, 1989 | Abandoned |
Array
(
[id] => 2877771
[patent_doc_number] => 05097447
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-17
[patent_title] => 'Semiconductor memory device having a serial access memory'
[patent_app_type] => 1
[patent_app_number] => 7/408028
[patent_app_country] => US
[patent_app_date] => 1989-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 30
[patent_no_of_words] => 5735
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/097/05097447.pdf
[firstpage_image] =>[orig_patent_app_number] => 408028
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/408028 | Semiconductor memory device having a serial access memory | Sep 14, 1989 | Issued |
Array
(
[id] => 2605316
[patent_doc_number] => 04975875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-04
[patent_title] => 'Static random access memory with tri-layer conductor construction over access transistors'
[patent_app_type] => 1
[patent_app_number] => 7/406598
[patent_app_country] => US
[patent_app_date] => 1989-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3475
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/975/04975875.pdf
[firstpage_image] =>[orig_patent_app_number] => 406598
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/406598 | Static random access memory with tri-layer conductor construction over access transistors | Sep 12, 1989 | Issued |
Array
(
[id] => 2779179
[patent_doc_number] => 04985867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-15
[patent_title] => 'Semiconductor memory circuit'
[patent_app_type] => 1
[patent_app_number] => 7/405026
[patent_app_country] => US
[patent_app_date] => 1989-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3350
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/985/04985867.pdf
[firstpage_image] =>[orig_patent_app_number] => 405026
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/405026 | Semiconductor memory circuit | Sep 10, 1989 | Issued |
| 07/403667 | FIRST-IN FIRST-OUT SEMICONDUCTOR MEMORY DEVICE | Sep 5, 1989 | Abandoned |
Array
(
[id] => 2998284
[patent_doc_number] => 05267200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-30
[patent_title] => 'Semiconductor memory device and operating method thereof with transfer transistor used as a holding means'
[patent_app_type] => 1
[patent_app_number] => 7/399946
[patent_app_country] => US
[patent_app_date] => 1989-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7929
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/267/05267200.pdf
[firstpage_image] =>[orig_patent_app_number] => 399946
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/399946 | Semiconductor memory device and operating method thereof with transfer transistor used as a holding means | Aug 30, 1989 | Issued |
Array
(
[id] => 2716924
[patent_doc_number] => 05014244
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-07
[patent_title] => 'Integrated memory circuit with parallel and serial input and output'
[patent_app_type] => 1
[patent_app_number] => 7/398816
[patent_app_country] => US
[patent_app_date] => 1989-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4050
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/014/05014244.pdf
[firstpage_image] =>[orig_patent_app_number] => 398816
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/398816 | Integrated memory circuit with parallel and serial input and output | Aug 24, 1989 | Issued |
Array
(
[id] => 2664720
[patent_doc_number] => 04972370
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-20
[patent_title] => 'Three-dimensional memory element and memory device'
[patent_app_type] => 1
[patent_app_number] => 7/398271
[patent_app_country] => US
[patent_app_date] => 1989-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 8431
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/972/04972370.pdf
[firstpage_image] =>[orig_patent_app_number] => 398271
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/398271 | Three-dimensional memory element and memory device | Aug 23, 1989 | Issued |
Array
(
[id] => 2598545
[patent_doc_number] => 04970686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-13
[patent_title] => 'Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells'
[patent_app_type] => 1
[patent_app_number] => 7/396246
[patent_app_country] => US
[patent_app_date] => 1989-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4421
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/970/04970686.pdf
[firstpage_image] =>[orig_patent_app_number] => 396246
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/396246 | Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells | Aug 20, 1989 | Issued |
Array
(
[id] => 2889783
[patent_doc_number] => 05159681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-27
[patent_title] => 'Page printer memory allocation'
[patent_app_type] => 1
[patent_app_number] => 7/392492
[patent_app_country] => US
[patent_app_date] => 1989-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 5067
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 410
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/159/05159681.pdf
[firstpage_image] =>[orig_patent_app_number] => 392492
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/392492 | Page printer memory allocation | Aug 10, 1989 | Issued |
| 07/393666 | INTEGRATED SEMICONDUCTOR CIRCUIT | Aug 10, 1989 | Abandoned |