
Jessica S. Manno
Supervisory Patent Examiner (ID: 4994, Phone: (571)272-2339 , Office: P/2828 )
| Most Active Art Unit | 2873 |
| Art Unit(s) | 2828, 2873, 2898 |
| Total Applications | 691 |
| Issued Applications | 505 |
| Pending Applications | 42 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1184612
[patent_doc_number] => 06738069
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-18
[patent_title] => 'Efficient graphics state management for zone rendering'
[patent_app_type] => B2
[patent_app_number] => 10/039007
[patent_app_country] => US
[patent_app_date] => 2001-12-31
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[pdf_file] => patents/06/738/06738069.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/039007 | Efficient graphics state management for zone rendering | Dec 30, 2001 | Issued |
Array
(
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[patent_doc_number] => 06747657
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[patent_issue_date] => 2004-06-08
[patent_title] => 'Depth write disable for zone rendering'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038814 | Depth write disable for zone rendering | Dec 30, 2001 | Issued |
Array
(
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[patent_issue_date] => 2004-02-24
[patent_title] => 'Method and apparatus for address re-mapping'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038456 | Method and apparatus for address re-mapping | Dec 30, 2001 | Issued |
Array
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[patent_doc_number] => 20030123089
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[patent_kind] => A1
[patent_issue_date] => 2003-07-03
[patent_title] => 'Graphics state bandwidth reduction for zone rendering'
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038922 | Graphics state bandwidth reduction for zone rendering | Dec 30, 2001 | Abandoned |
Array
(
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[patent_issue_date] => 2006-02-14
[patent_title] => 'Dual memory channel interleaving for graphics and video'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/033439 | Dual memory channel interleaving for graphics and video | Dec 27, 2001 | Issued |
Array
(
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[patent_doc_number] => 06791554
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[patent_issue_date] => 2004-09-14
[patent_title] => 'I/O node for a computer system including an integrated graphics engine'
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 10025813
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/025813 | Memory control apparatus and method | Dec 25, 2001 | Issued |
Array
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[id] => 1190608
[patent_doc_number] => 06734868
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[patent_issue_date] => 2004-05-11
[patent_title] => 'Address generator for video pixel reordering in reflective LCD'
[patent_app_type] => B2
[patent_app_number] => 10/028380
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[pdf_file] => patents/06/734/06734868.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/028380 | Address generator for video pixel reordering in reflective LCD | Dec 20, 2001 | Issued |
Array
(
[id] => 6681541
[patent_doc_number] => 20030117405
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[patent_issue_date] => 2003-06-26
[patent_title] => 'Systems and methods for performing memory management operations to provide displays of complex virtual environments'
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Array
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Array
(
[id] => 6667265
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[patent_title] => 'VGA quad device and apparatuses including same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/024780 | VGA quad device and apparatuses including same | Dec 18, 2001 | Abandoned |
Array
(
[id] => 6698050
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Array
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