
Jezia Riley
Examiner (ID: 3542, Phone: (571)272-0786 , Office: P/1637 )
| Most Active Art Unit | 1637 |
| Art Unit(s) | 1634, 1656, 1809, 1621, 1635, 1637, 1681, 1655 |
| Total Applications | 2692 |
| Issued Applications | 2037 |
| Pending Applications | 263 |
| Abandoned Applications | 414 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20353398
[patent_doc_number] => 20250350250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => SYSTEMS AND METHODS FOR DRIVING SEMICONDUCTOR DEVICES AND SENSING DEVICE PARAMETERS
[patent_app_type] => utility
[patent_app_number] => 19/189893
[patent_app_country] => US
[patent_app_date] => 2025-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5818
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19189893
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/189893 | SYSTEMS AND METHODS FOR DRIVING SEMICONDUCTOR DEVICES AND SENSING DEVICE PARAMETERS | Apr 24, 2025 | Pending |
Array
(
[id] => 20096881
[patent_doc_number] => 20250226817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-10
[patent_title] => CONFIGURATION OF AGGRESSOR INTEGRATED CIRCUIT TO PREVENT SPUR INTERFERENCE AT VICTIM INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 19/088823
[patent_app_country] => US
[patent_app_date] => 2025-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3293
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19088823
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/088823 | CONFIGURATION OF AGGRESSOR INTEGRATED CIRCUIT TO PREVENT SPUR INTERFERENCE AT VICTIM INTEGRATED CIRCUIT | Mar 23, 2025 | Pending |
Array
(
[id] => 20284634
[patent_doc_number] => 20250309876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => RADIO-FREQUENCY CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 19/085206
[patent_app_country] => US
[patent_app_date] => 2025-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9637
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19085206
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/085206 | RADIO-FREQUENCY CIRCUIT | Mar 19, 2025 | Pending |
Array
(
[id] => 20154012
[patent_doc_number] => 20250253850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => VOLTAGE PROVISION CIRCUITS WITH CORE TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 19/084022
[patent_app_country] => US
[patent_app_date] => 2025-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3271
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19084022
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/084022 | VOLTAGE PROVISION CIRCUITS WITH CORE TRANSISTORS | Mar 18, 2025 | Pending |
Array
(
[id] => 20251779
[patent_doc_number] => 20250300648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => Data receiving apparatus and method having data valid window expanding mechanism
[patent_app_type] => utility
[patent_app_number] => 19/082748
[patent_app_country] => US
[patent_app_date] => 2025-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 301
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19082748
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/082748 | Data receiving apparatus and method having data valid window expanding mechanism | Mar 17, 2025 | Pending |
Array
(
[id] => 20251789
[patent_doc_number] => 20250300658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => VOLTAGE LEVEL SHIFTER
[patent_app_type] => utility
[patent_app_number] => 19/078289
[patent_app_country] => US
[patent_app_date] => 2025-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19078289
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/078289 | VOLTAGE LEVEL SHIFTER | Mar 12, 2025 | Pending |
Array
(
[id] => 20064262
[patent_doc_number] => 20250202484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => SYNCHRONIZATION OF SENSOR OUTPUT SAMPLES
[patent_app_type] => utility
[patent_app_number] => 19/067150
[patent_app_country] => US
[patent_app_date] => 2025-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19067150
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/067150 | SYNCHRONIZATION OF SENSOR OUTPUT SAMPLES | Feb 27, 2025 | Pending |
Array
(
[id] => 20054554
[patent_doc_number] => 20250192776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 19/056488
[patent_app_country] => US
[patent_app_date] => 2025-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19056488
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/056488 | INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING SAME | Feb 17, 2025 | Pending |
Array
(
[id] => 20210050
[patent_doc_number] => 20250279770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-04
[patent_title] => METHOD AND DEVICE FOR REDUCING FILTER DELAY SPREAD IN INTERFACE IP
[patent_app_type] => utility
[patent_app_number] => 19/056472
[patent_app_country] => US
[patent_app_date] => 2025-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19056472
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/056472 | METHOD AND DEVICE FOR REDUCING FILTER DELAY SPREAD IN INTERFACE IP | Feb 17, 2025 | Pending |
Array
(
[id] => 20054545
[patent_doc_number] => 20250192767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => LOW LEAKAGE CURRENT FEEDTHROUGH SWITCH
[patent_app_type] => utility
[patent_app_number] => 19/047800
[patent_app_country] => US
[patent_app_date] => 2025-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9189
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047800
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047800 | LOW LEAKAGE CURRENT FEEDTHROUGH SWITCH | Feb 6, 2025 | Pending |
Array
(
[id] => 20180941
[patent_doc_number] => 20250264899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => BIASING CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 19/047066
[patent_app_country] => US
[patent_app_date] => 2025-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1205
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047066
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047066 | BIASING CIRCUIT | Feb 5, 2025 | Pending |
Array
(
[id] => 20654584
[patent_doc_number] => 20260106609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-16
[patent_title] => Low-Side Switch Circuit, Method for Controlling the Same, Integrated Circuit, and Electronic Device
[patent_app_type] => utility
[patent_app_number] => 19/047313
[patent_app_country] => US
[patent_app_date] => 2025-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7046
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047313
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047313 | Low-Side Switch Circuit, Method for Controlling the Same, Integrated Circuit, and Electronic Device | Feb 5, 2025 | Pending |
Array
(
[id] => 20043734
[patent_doc_number] => 20250181956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => INFORMATION PROCESSING DEVICE, METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM
[patent_app_type] => utility
[patent_app_number] => 19/047117
[patent_app_country] => US
[patent_app_date] => 2025-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4741
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047117
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/047117 | INFORMATION PROCESSING DEVICE, METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM | Feb 5, 2025 | Pending |
Array
(
[id] => 20180938
[patent_doc_number] => 20250264896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => BANDGAP REFERENCE CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 19/045558
[patent_app_country] => US
[patent_app_date] => 2025-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19045558
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/045558 | BANDGAP REFERENCE CIRCUIT | Feb 4, 2025 | Pending |
Array
(
[id] => 20037147
[patent_doc_number] => 20250175369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => COMMUNICATION APPARATUS AND COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 19/040361
[patent_app_country] => US
[patent_app_date] => 2025-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1035
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19040361
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/040361 | COMMUNICATION APPARATUS AND COMMUNICATION SYSTEM | Jan 28, 2025 | Pending |
Array
(
[id] => 20140057
[patent_doc_number] => 20250247101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => PHASE LOCK LOOP WITH IMPROVED PERFORMANCES AND RELATED METHOD
[patent_app_type] => utility
[patent_app_number] => 19/034687
[patent_app_country] => US
[patent_app_date] => 2025-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9298
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19034687
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/034687 | PHASE LOCK LOOP WITH IMPROVED PERFORMANCES AND RELATED METHOD | Jan 22, 2025 | Pending |
Array
(
[id] => 20154001
[patent_doc_number] => 20250253839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => LOAD SWITCHING DEVICE
[patent_app_type] => utility
[patent_app_number] => 19/035149
[patent_app_country] => US
[patent_app_date] => 2025-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19035149
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/035149 | LOAD SWITCHING DEVICE | Jan 22, 2025 | Pending |
Array
(
[id] => 20474630
[patent_doc_number] => 20260016851
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-15
[patent_title] => HIGH-SPEED DELTA SIGMA MODULATORS
[patent_app_type] => utility
[patent_app_number] => 19/033536
[patent_app_country] => US
[patent_app_date] => 2025-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19033536
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/033536 | HIGH-SPEED DELTA SIGMA MODULATORS | Jan 21, 2025 | Pending |
Array
(
[id] => 20140044
[patent_doc_number] => 20250247088
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => Switch circuit
[patent_app_type] => utility
[patent_app_number] => 19/032473
[patent_app_country] => US
[patent_app_date] => 2025-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 326
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19032473
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/032473 | Switch circuit | Jan 20, 2025 | Pending |
Array
(
[id] => 20410468
[patent_doc_number] => 20250379577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-11
[patent_title] => RADIO-FREQUENCY SWITCH CIRCUIT SUPPORTING HIGH-POWER MODE, CHIP, AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 19/031985
[patent_app_country] => US
[patent_app_date] => 2025-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19031985
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/031985 | RADIO-FREQUENCY SWITCH CIRCUIT SUPPORTING HIGH-POWER MODE, CHIP, AND ELECTRONIC DEVICE | Jan 17, 2025 | Pending |