Search

Jhere M Rowland

Examiner (ID: 14039)

Most Active Art Unit
2666
Art Unit(s)
2666, 2624
Total Applications
72
Issued Applications
43
Pending Applications
0
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5606114 [patent_doc_number] => 20060267630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/442958 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5738 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267630.pdf [firstpage_image] =>[orig_patent_app_number] => 11442958 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/442958
Semiconductor integrated circuit and construction using densely integrated cells May 30, 2006 Issued
Array ( [id] => 5780648 [patent_doc_number] => 20060202713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE CHARACTERISTICS OF CIRCUITRY IN PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 11/420736 [patent_app_country] => US [patent_app_date] => 2006-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12200 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20060202713.pdf [firstpage_image] =>[orig_patent_app_number] => 11420736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420736
APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE CHARACTERISTICS OF CIRCUITRY IN PROGRAMMABLE LOGIC DEVICES May 26, 2006 Abandoned
Array ( [id] => 4605178 [patent_doc_number] => 07986160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/420737 [patent_app_country] => US [patent_app_date] => 2006-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 12388 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986160.pdf [firstpage_image] =>[orig_patent_app_number] => 11420737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420737
Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices May 26, 2006 Issued
Array ( [id] => 364016 [patent_doc_number] => 07482832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Termination circuit and semiconductor device comprising that termination circuit' [patent_app_type] => utility [patent_app_number] => 11/434715 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5762 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482832.pdf [firstpage_image] =>[orig_patent_app_number] => 11434715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/434715
Termination circuit and semiconductor device comprising that termination circuit May 16, 2006 Issued
Array ( [id] => 821045 [patent_doc_number] => 07408380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method and apparatus for a redundant transceiver architecture' [patent_app_type] => utility [patent_app_number] => 11/435427 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408380.pdf [firstpage_image] =>[orig_patent_app_number] => 11435427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435427
Method and apparatus for a redundant transceiver architecture May 15, 2006 Issued
Array ( [id] => 928873 [patent_doc_number] => 07315185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver' [patent_app_type] => utility [patent_app_number] => 11/434960 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315185.pdf [firstpage_image] =>[orig_patent_app_number] => 11434960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/434960
Low voltage differential signal receiver and methods of calibrating a termination resistance of a low voltage differential signal receiver May 15, 2006 Issued
Array ( [id] => 5623351 [patent_doc_number] => 20060261856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Semiconductor chip and semiconductor device incorporating the same' [patent_app_type] => utility [patent_app_number] => 11/434263 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3349 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261856.pdf [firstpage_image] =>[orig_patent_app_number] => 11434263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/434263
Semiconductor chip and semiconductor device incorporating the same May 15, 2006 Abandoned
Array ( [id] => 367113 [patent_doc_number] => 07479798 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-20 [patent_title] => 'Selectively disabled output' [patent_app_type] => utility [patent_app_number] => 11/435416 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4306 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479798.pdf [firstpage_image] =>[orig_patent_app_number] => 11435416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435416
Selectively disabled output May 15, 2006 Issued
Array ( [id] => 4997949 [patent_doc_number] => 20070040583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/433622 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4389 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040583.pdf [firstpage_image] =>[orig_patent_app_number] => 11433622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433622
Semiconductor device May 11, 2006 Issued
Array ( [id] => 5606118 [patent_doc_number] => 20060267634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Low voltage differential signaling receiver with a digital resistor unit and low voltage differential signaling interface system having the same' [patent_app_type] => utility [patent_app_number] => 11/432447 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6043 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267634.pdf [firstpage_image] =>[orig_patent_app_number] => 11432447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432447
Low voltage differential signaling receiver with a digital resistor unit and low voltage differential signaling interface system having the same May 10, 2006 Issued
Array ( [id] => 5208599 [patent_doc_number] => 20070247183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'LOGIC-LATCHING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS' [patent_app_type] => utility [patent_app_number] => 11/308823 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4181 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247183.pdf [firstpage_image] =>[orig_patent_app_number] => 11308823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308823
LOGIC-LATCHING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS May 10, 2006 Abandoned
Array ( [id] => 5241275 [patent_doc_number] => 20070019766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Clock circuitry for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/432419 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5065 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019766.pdf [firstpage_image] =>[orig_patent_app_number] => 11432419 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432419
Clock circuitry for programmable logic devices May 9, 2006 Issued
Array ( [id] => 364015 [patent_doc_number] => 07482831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Soft error tolerant flip flops' [patent_app_type] => utility [patent_app_number] => 11/431802 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482831.pdf [firstpage_image] =>[orig_patent_app_number] => 11431802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/431802
Soft error tolerant flip flops May 9, 2006 Issued
Array ( [id] => 5111052 [patent_doc_number] => 20070194967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'IMPEDANCE MATCH CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/308788 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3727 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194967.pdf [firstpage_image] =>[orig_patent_app_number] => 11308788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308788
Impedance match circuit May 3, 2006 Issued
Array ( [id] => 583816 [patent_doc_number] => 07456656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/398545 [patent_app_country] => US [patent_app_date] => 2006-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5782 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456656.pdf [firstpage_image] =>[orig_patent_app_number] => 11398545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398545
Semiconductor device and method of manufacturing the same Apr 5, 2006 Issued
Array ( [id] => 580850 [patent_doc_number] => 07459931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Programmable logic devices with transparent field reconfiguration' [patent_app_type] => utility [patent_app_number] => 11/398437 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7350 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459931.pdf [firstpage_image] =>[orig_patent_app_number] => 11398437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398437
Programmable logic devices with transparent field reconfiguration Apr 4, 2006 Issued
Array ( [id] => 282357 [patent_doc_number] => 07554358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Programmable logic devices with user non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/397985 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5536 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554358.pdf [firstpage_image] =>[orig_patent_app_number] => 11397985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397985
Programmable logic devices with user non-volatile memory Apr 4, 2006 Issued
Array ( [id] => 405135 [patent_doc_number] => 07288969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-30 [patent_title] => 'Zero clock delay metastability filtering circuit' [patent_app_type] => utility [patent_app_number] => 11/397570 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3483 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288969.pdf [firstpage_image] =>[orig_patent_app_number] => 11397570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397570
Zero clock delay metastability filtering circuit Apr 4, 2006 Issued
Array ( [id] => 873760 [patent_doc_number] => 07362136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Dual voltage single gate oxide I/O circuit with high voltage stress tolerance' [patent_app_type] => utility [patent_app_number] => 11/397213 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3614 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362136.pdf [firstpage_image] =>[orig_patent_app_number] => 11397213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397213
Dual voltage single gate oxide I/O circuit with high voltage stress tolerance Apr 3, 2006 Issued
Array ( [id] => 282359 [patent_doc_number] => 07554360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'High speed level shifter circuit in advanced CMOS technology' [patent_app_type] => utility [patent_app_number] => 11/398387 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4543 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554360.pdf [firstpage_image] =>[orig_patent_app_number] => 11398387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398387
High speed level shifter circuit in advanced CMOS technology Apr 3, 2006 Issued
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