Search

Jhere M Rowland

Examiner (ID: 14039)

Most Active Art Unit
2666
Art Unit(s)
2666, 2624
Total Applications
72
Issued Applications
43
Pending Applications
0
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 205598 [patent_doc_number] => 07629813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Dynamic refreshed receiver for proximity communication' [patent_app_type] => utility [patent_app_number] => 11/327530 [patent_app_country] => US [patent_app_date] => 2006-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3787 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629813.pdf [firstpage_image] =>[orig_patent_app_number] => 11327530 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/327530
Dynamic refreshed receiver for proximity communication Jan 4, 2006 Issued
Array ( [id] => 5117361 [patent_doc_number] => 20070139075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Combined multiplexor/flop' [patent_app_type] => utility [patent_app_number] => 11/304165 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6259 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139075.pdf [firstpage_image] =>[orig_patent_app_number] => 11304165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304165
Combined multiplex or/flop Dec 14, 2005 Issued
Array ( [id] => 923372 [patent_doc_number] => 07319344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-15 [patent_title] => 'Pulsed flop with embedded logic' [patent_app_type] => utility [patent_app_number] => 11/304855 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6236 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/319/07319344.pdf [firstpage_image] =>[orig_patent_app_number] => 11304855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304855
Pulsed flop with embedded logic Dec 14, 2005 Issued
Array ( [id] => 5646845 [patent_doc_number] => 20060132577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Circuit topology for high-speed printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/291756 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1609 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20060132577.pdf [firstpage_image] =>[orig_patent_app_number] => 11291756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/291756
Circuit topology for high-speed printed circuit board Nov 30, 2005 Abandoned
Array ( [id] => 5746099 [patent_doc_number] => 20060109029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Logic circuit' [patent_app_type] => utility [patent_app_number] => 11/285285 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6814 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109029.pdf [firstpage_image] =>[orig_patent_app_number] => 11285285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285285
Logic circuit Nov 22, 2005 Issued
Array ( [id] => 5838906 [patent_doc_number] => 20060119392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Semiconductor integrated circuit and layout design method thereof, and standard cell' [patent_app_type] => utility [patent_app_number] => 11/285020 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5313 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119392.pdf [firstpage_image] =>[orig_patent_app_number] => 11285020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285020
Semiconductor integrated circuit and layout design method thereof, and standard cell Nov 22, 2005 Abandoned
Array ( [id] => 444080 [patent_doc_number] => 07256622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'AND, OR, NAND, and NOR logical gates' [patent_app_type] => utility [patent_app_number] => 11/284562 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 3566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256622.pdf [firstpage_image] =>[orig_patent_app_number] => 11284562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284562
AND, OR, NAND, and NOR logical gates Nov 21, 2005 Issued
Array ( [id] => 5746101 [patent_doc_number] => 20060109031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Complementary pass-transistor logic circuit and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/283852 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4860 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109031.pdf [firstpage_image] =>[orig_patent_app_number] => 11283852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/283852
Complementary pass-transistor logic circuit and semiconductor device Nov 21, 2005 Issued
Array ( [id] => 853741 [patent_doc_number] => 07378871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Programmable device with structure for storing configuration information' [patent_app_type] => utility [patent_app_number] => 11/264138 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4807 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/378/07378871.pdf [firstpage_image] =>[orig_patent_app_number] => 11264138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264138
Programmable device with structure for storing configuration information Nov 1, 2005 Issued
Array ( [id] => 377529 [patent_doc_number] => 07312631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-25 [patent_title] => 'Structures and methods for avoiding hold time violations in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/264405 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6511 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312631.pdf [firstpage_image] =>[orig_patent_app_number] => 11264405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264405
Structures and methods for avoiding hold time violations in a programmable logic device Oct 31, 2005 Issued
Array ( [id] => 824119 [patent_doc_number] => 07405593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Systems and methods for transmitting signals across integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 11/265550 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8870 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405593.pdf [firstpage_image] =>[orig_patent_app_number] => 11265550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265550
Systems and methods for transmitting signals across integrated circuit chips Oct 31, 2005 Issued
Array ( [id] => 73081 [patent_doc_number] => 07755387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'FPGA having a direct routing structure' [patent_app_type] => utility [patent_app_number] => 11/264674 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/755/07755387.pdf [firstpage_image] =>[orig_patent_app_number] => 11264674 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264674
FPGA having a direct routing structure Oct 31, 2005 Issued
Array ( [id] => 133095 [patent_doc_number] => 07701247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-20 [patent_title] => 'Data buffering with readout latency for single-event upset tolerant operation' [patent_app_type] => utility [patent_app_number] => 11/261685 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4187 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701247.pdf [firstpage_image] =>[orig_patent_app_number] => 11261685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261685
Data buffering with readout latency for single-event upset tolerant operation Oct 27, 2005 Issued
Array ( [id] => 5214106 [patent_doc_number] => 20070103186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection' [patent_app_type] => utility [patent_app_number] => 11/263138 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4984 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103186.pdf [firstpage_image] =>[orig_patent_app_number] => 11263138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263138
Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection Oct 26, 2005 Issued
Array ( [id] => 5054774 [patent_doc_number] => 20070057695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Semiconductor memory chip with re-drive unit for electrical signals' [patent_app_type] => utility [patent_app_number] => 11/226456 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1980 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057695.pdf [firstpage_image] =>[orig_patent_app_number] => 11226456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226456
Semiconductor memory chip with re-drive unit for electrical signals Sep 14, 2005 Abandoned
Array ( [id] => 447979 [patent_doc_number] => 07253656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Calibration circuit for a driver control circuit, and driver control circuit' [patent_app_type] => utility [patent_app_number] => 11/226901 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6595 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253656.pdf [firstpage_image] =>[orig_patent_app_number] => 11226901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226901
Calibration circuit for a driver control circuit, and driver control circuit Sep 13, 2005 Issued
Array ( [id] => 415746 [patent_doc_number] => 07279932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/226585 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2424 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279932.pdf [firstpage_image] =>[orig_patent_app_number] => 11226585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226585
Semiconductor integrated circuit device Sep 13, 2005 Issued
Array ( [id] => 304108 [patent_doc_number] => 07535249 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Authentication for information provided to an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/223388 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6207 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535249.pdf [firstpage_image] =>[orig_patent_app_number] => 11223388 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223388
Authentication for information provided to an integrated circuit Sep 8, 2005 Issued
Array ( [id] => 5181103 [patent_doc_number] => 20070052445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Pre-buffer level shifter and input/output buffer apparatus' [patent_app_type] => utility [patent_app_number] => 11/223742 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4032 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052445.pdf [firstpage_image] =>[orig_patent_app_number] => 11223742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223742
Pre-buffer level shifter and input/output buffer apparatus Sep 7, 2005 Issued
Array ( [id] => 5086565 [patent_doc_number] => 20070276616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Identifying a Reference Point in a Signal' [patent_app_type] => utility [patent_app_number] => 11/573289 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20070276616.pdf [firstpage_image] =>[orig_patent_app_number] => 11573289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/573289
Identifying a Reference Point in a Signal Aug 7, 2005 Abandoned
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