Jhere M Rowland
Examiner (ID: 14039)
Most Active Art Unit | 2666 |
Art Unit(s) | 2666, 2624 |
Total Applications | 72 |
Issued Applications | 43 |
Pending Applications | 0 |
Abandoned Applications | 29 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 205598
[patent_doc_number] => 07629813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'Dynamic refreshed receiver for proximity communication'
[patent_app_type] => utility
[patent_app_number] => 11/327530
[patent_app_country] => US
[patent_app_date] => 2006-01-05
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[pdf_file] => patents/07/629/07629813.pdf
[firstpage_image] =>[orig_patent_app_number] => 11327530
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/327530 | Dynamic refreshed receiver for proximity communication | Jan 4, 2006 | Issued |
Array
(
[id] => 5117361
[patent_doc_number] => 20070139075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-21
[patent_title] => 'Combined multiplexor/flop'
[patent_app_type] => utility
[patent_app_number] => 11/304165
[patent_app_country] => US
[patent_app_date] => 2005-12-15
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[firstpage_image] =>[orig_patent_app_number] => 11304165
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/304165 | Combined multiplex or/flop | Dec 14, 2005 | Issued |
Array
(
[id] => 923372
[patent_doc_number] => 07319344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-15
[patent_title] => 'Pulsed flop with embedded logic'
[patent_app_type] => utility
[patent_app_number] => 11/304855
[patent_app_country] => US
[patent_app_date] => 2005-12-15
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[pdf_file] => patents/07/319/07319344.pdf
[firstpage_image] =>[orig_patent_app_number] => 11304855
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/304855 | Pulsed flop with embedded logic | Dec 14, 2005 | Issued |
Array
(
[id] => 5646845
[patent_doc_number] => 20060132577
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Circuit topology for high-speed printed circuit board'
[patent_app_type] => utility
[patent_app_number] => 11/291756
[patent_app_country] => US
[patent_app_date] => 2005-12-01
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[firstpage_image] =>[orig_patent_app_number] => 11291756
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/291756 | Circuit topology for high-speed printed circuit board | Nov 30, 2005 | Abandoned |
Array
(
[id] => 5746099
[patent_doc_number] => 20060109029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Logic circuit'
[patent_app_type] => utility
[patent_app_number] => 11/285285
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11285285
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/285285 | Logic circuit | Nov 22, 2005 | Issued |
Array
(
[id] => 5838906
[patent_doc_number] => 20060119392
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[patent_issue_date] => 2006-06-08
[patent_title] => 'Semiconductor integrated circuit and layout design method thereof, and standard cell'
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[pdf_file] => publications/A1/0119/20060119392.pdf
[firstpage_image] =>[orig_patent_app_number] => 11285020
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/285020 | Semiconductor integrated circuit and layout design method thereof, and standard cell | Nov 22, 2005 | Abandoned |
Array
(
[id] => 444080
[patent_doc_number] => 07256622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-14
[patent_title] => 'AND, OR, NAND, and NOR logical gates'
[patent_app_type] => utility
[patent_app_number] => 11/284562
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[patent_app_date] => 2005-11-22
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[pdf_file] => patents/07/256/07256622.pdf
[firstpage_image] =>[orig_patent_app_number] => 11284562
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/284562 | AND, OR, NAND, and NOR logical gates | Nov 21, 2005 | Issued |
Array
(
[id] => 5746101
[patent_doc_number] => 20060109031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Complementary pass-transistor logic circuit and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/283852
[patent_app_country] => US
[patent_app_date] => 2005-11-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11283852
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/283852 | Complementary pass-transistor logic circuit and semiconductor device | Nov 21, 2005 | Issued |
Array
(
[id] => 853741
[patent_doc_number] => 07378871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Programmable device with structure for storing configuration information'
[patent_app_type] => utility
[patent_app_number] => 11/264138
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[pdf_file] => patents/07/378/07378871.pdf
[firstpage_image] =>[orig_patent_app_number] => 11264138
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/264138 | Programmable device with structure for storing configuration information | Nov 1, 2005 | Issued |
Array
(
[id] => 377529
[patent_doc_number] => 07312631
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-12-25
[patent_title] => 'Structures and methods for avoiding hold time violations in a programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 11/264405
[patent_app_country] => US
[patent_app_date] => 2005-11-01
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[pdf_file] => patents/07/312/07312631.pdf
[firstpage_image] =>[orig_patent_app_number] => 11264405
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/264405 | Structures and methods for avoiding hold time violations in a programmable logic device | Oct 31, 2005 | Issued |
Array
(
[id] => 824119
[patent_doc_number] => 07405593
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-29
[patent_title] => 'Systems and methods for transmitting signals across integrated circuit chips'
[patent_app_type] => utility
[patent_app_number] => 11/265550
[patent_app_country] => US
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[pdf_file] => patents/07/405/07405593.pdf
[firstpage_image] =>[orig_patent_app_number] => 11265550
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/265550 | Systems and methods for transmitting signals across integrated circuit chips | Oct 31, 2005 | Issued |
Array
(
[id] => 73081
[patent_doc_number] => 07755387
[patent_country] => US
[patent_kind] => B2
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[patent_title] => 'FPGA having a direct routing structure'
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[patent_app_number] => 11/264674
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[firstpage_image] =>[orig_patent_app_number] => 11264674
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/264674 | FPGA having a direct routing structure | Oct 31, 2005 | Issued |
Array
(
[id] => 133095
[patent_doc_number] => 07701247
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[patent_title] => 'Data buffering with readout latency for single-event upset tolerant operation'
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[firstpage_image] =>[orig_patent_app_number] => 11261685
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/261685 | Data buffering with readout latency for single-event upset tolerant operation | Oct 27, 2005 | Issued |
Array
(
[id] => 5214106
[patent_doc_number] => 20070103186
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[patent_title] => 'Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/263138 | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection | Oct 26, 2005 | Issued |
Array
(
[id] => 5054774
[patent_doc_number] => 20070057695
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[patent_issue_date] => 2007-03-15
[patent_title] => 'Semiconductor memory chip with re-drive unit for electrical signals'
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[firstpage_image] =>[orig_patent_app_number] => 11226456
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226456 | Semiconductor memory chip with re-drive unit for electrical signals | Sep 14, 2005 | Abandoned |
Array
(
[id] => 447979
[patent_doc_number] => 07253656
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[patent_title] => 'Calibration circuit for a driver control circuit, and driver control circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11226901
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226901 | Calibration circuit for a driver control circuit, and driver control circuit | Sep 13, 2005 | Issued |
Array
(
[id] => 415746
[patent_doc_number] => 07279932
[patent_country] => US
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[patent_issue_date] => 2007-10-09
[patent_title] => 'Semiconductor integrated circuit device'
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Array
(
[id] => 304108
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[patent_title] => 'Authentication for information provided to an integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223388 | Authentication for information provided to an integrated circuit | Sep 8, 2005 | Issued |
Array
(
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Array
(
[id] => 5086565
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[patent_title] => 'Identifying a Reference Point in a Signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/573289 | Identifying a Reference Point in a Signal | Aug 7, 2005 | Abandoned |