
Ji H. Bae
Examiner (ID: 6530, Phone: (571)272-7181 , Office: P/2115 )
| Most Active Art Unit | 2115 |
| Art Unit(s) | 2115, 2187, 2118, 2176 |
| Total Applications | 971 |
| Issued Applications | 764 |
| Pending Applications | 63 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14106455
[patent_doc_number] => 20190094903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => SECURITY CONTROL AND METHOD FOR OPERATING A SECURITY CONTROL
[patent_app_type] => utility
[patent_app_number] => 16/086349
[patent_app_country] => US
[patent_app_date] => 2017-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4206
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086349
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/086349 | Security control and method for operating a security control | Feb 13, 2017 | Issued |
Array
(
[id] => 11651154
[patent_doc_number] => 20170147055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'SYSTEMS AND METHODS FOR PROVIDING LOCAL HARDWARE LIMIT MANAGEMENT AND ENFORCEMENT'
[patent_app_type] => utility
[patent_app_number] => 15/403130
[patent_app_country] => US
[patent_app_date] => 2017-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7434
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403130
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/403130 | SYSTEMS AND METHODS FOR PROVIDING LOCAL HARDWARE LIMIT MANAGEMENT AND ENFORCEMENT | Jan 9, 2017 | Abandoned |
Array
(
[id] => 11606164
[patent_doc_number] => 20170123467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'Adaptive Algorithm For Thermal Throttling Of Multi-Core Processors With Non-Homogeneous Performance States'
[patent_app_type] => utility
[patent_app_number] => 15/401276
[patent_app_country] => US
[patent_app_date] => 2017-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13258
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401276
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/401276 | Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states | Jan 8, 2017 | Issued |
Array
(
[id] => 12874495
[patent_doc_number] => 20180183340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => DYNAMIC LEARNING OF VOLTAGE SOURCE CAPABILITIES
[patent_app_type] => utility
[patent_app_number] => 15/392047
[patent_app_country] => US
[patent_app_date] => 2016-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392047
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/392047 | Dynamic learning of voltage source capabilities | Dec 27, 2016 | Issued |
Array
(
[id] => 12868018
[patent_doc_number] => 20180181181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => DIFFERENTIAL CURRENT MONITORING OF MULTIPLE CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 15/392766
[patent_app_country] => US
[patent_app_date] => 2016-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3138
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392766
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/392766 | DIFFERENTIAL CURRENT MONITORING OF MULTIPLE CIRCUITS | Dec 27, 2016 | Abandoned |
Array
(
[id] => 11717283
[patent_doc_number] => 20170185782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-29
[patent_title] => 'ELECTRONIC APPARATUS, METHOD AND STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 15/389329
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5812
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389329
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/389329 | Method, apparatus, and medium for using a stored pre-boot authentication password to skip a pre-boot authentication step | Dec 21, 2016 | Issued |
Array
(
[id] => 12852055
[patent_doc_number] => 20180175858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => ADAPTIVE POWER SAVING IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) IN OPTICAL MODULE
[patent_app_type] => utility
[patent_app_number] => 15/381278
[patent_app_country] => US
[patent_app_date] => 2016-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6942
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15381278
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/381278 | Adaptive power saving in field programmable gate array (FPGA) in optical module | Dec 15, 2016 | Issued |
Array
(
[id] => 13626451
[patent_doc_number] => 20180364777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-20
[patent_title] => DYNAMIC CONNECTION OF THE ELECTRIC POWER SUPPLY
[patent_app_type] => utility
[patent_app_number] => 16/063037
[patent_app_country] => US
[patent_app_date] => 2016-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6054
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16063037
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/063037 | DYNAMIC CONNECTION OF THE ELECTRIC POWER SUPPLY | Dec 15, 2016 | Abandoned |
Array
(
[id] => 11516633
[patent_doc_number] => 20170083707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'MEDIATED SECURE BOOT FOR SINGLE OR MULTICORE PROCESSORS'
[patent_app_type] => utility
[patent_app_number] => 15/369299
[patent_app_country] => US
[patent_app_date] => 2016-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4683
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369299
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/369299 | Mediated secure boot for single or multicore processors | Dec 4, 2016 | Issued |
Array
(
[id] => 14935069
[patent_doc_number] => 20190303172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => INFORMATION PROCESSING APPARATUS, DEVICE ASSIGNMENT METHOD, AND COMPUTER READABLE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 16/335627
[patent_app_country] => US
[patent_app_date] => 2016-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16335627
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/335627 | INFORMATION PROCESSING APPARATUS, DEVICE ASSIGNMENT METHOD, AND COMPUTER READABLE MEDIUM | Nov 15, 2016 | Abandoned |
Array
(
[id] => 11591306
[patent_doc_number] => 20170115717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'POWER MANAGEMENT INTEGRATED CIRCUIT INTEGRATING FIELD EFFECT TRANSISTORS AND PROGRAMMABLE FABRIC'
[patent_app_type] => utility
[patent_app_number] => 15/336146
[patent_app_country] => US
[patent_app_date] => 2016-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8633
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336146
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/336146 | Power management integrated circuit integrating field effect transistors and programmable fabric | Oct 26, 2016 | Issued |
Array
(
[id] => 14265301
[patent_doc_number] => 10282214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => System and method for power management of a plurality of circuit islands
[patent_app_type] => utility
[patent_app_number] => 15/333704
[patent_app_country] => US
[patent_app_date] => 2016-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6523
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333704
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/333704 | System and method for power management of a plurality of circuit islands | Oct 24, 2016 | Issued |
Array
(
[id] => 11606171
[patent_doc_number] => 20170123473
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'CONTROL APPARATUS THAT CONTROLS A MEMORY AND POWER SAVING CONTROL METHOD FOR THE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 15/333712
[patent_app_country] => US
[patent_app_date] => 2016-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5059
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333712
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/333712 | Control apparatus that controls a memory and power saving control method for the memory | Oct 24, 2016 | Issued |
Array
(
[id] => 14824705
[patent_doc_number] => 10409357
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-09-10
[patent_title] => Command-oriented low power control method of high-bandwidth-memory system
[patent_app_type] => utility
[patent_app_number] => 15/282979
[patent_app_country] => US
[patent_app_date] => 2016-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6404
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282979
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/282979 | Command-oriented low power control method of high-bandwidth-memory system | Sep 29, 2016 | Issued |
Array
(
[id] => 13894631
[patent_doc_number] => 10199873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-05
[patent_title] => Wireless power utilization in a local computing environment
[patent_app_type] => utility
[patent_app_number] => 15/279367
[patent_app_country] => US
[patent_app_date] => 2016-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5148
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15279367
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/279367 | Wireless power utilization in a local computing environment | Sep 27, 2016 | Issued |
Array
(
[id] => 14505833
[patent_doc_number] => 20190196571
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2019-06-27
[patent_title] => OPERATION METHODS OF COMMUNICATION NODE IN NETWORK
[patent_app_type] => utility
[patent_app_number] => 15/258379
[patent_app_country] => US
[patent_app_date] => 2016-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8952
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258379
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/258379 | Operation methods of communication node in network | Sep 6, 2016 | Issued |
Array
(
[id] => 14505833
[patent_doc_number] => 20190196571
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2019-06-27
[patent_title] => OPERATION METHODS OF COMMUNICATION NODE IN NETWORK
[patent_app_type] => utility
[patent_app_number] => 15/258379
[patent_app_country] => US
[patent_app_date] => 2016-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8952
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258379
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/258379 | Operation methods of communication node in network | Sep 6, 2016 | Issued |
Array
(
[id] => 11386410
[patent_doc_number] => 20170012466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-12
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/216513
[patent_app_country] => US
[patent_app_date] => 2016-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8348
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15216513
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/216513 | Semiconductor integrated circuit with shutoff control for plural power domains | Jul 20, 2016 | Issued |
Array
(
[id] => 11365998
[patent_doc_number] => 20170003979
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-05
[patent_title] => 'METHOD FOR THE CONFIGURATION OF ELECTRONIC DEVICES, IN PARTICULAR FOR THE CONFIGURATION OF COMPONENTS OF AN ACCESS CONTROL SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/198163
[patent_app_country] => US
[patent_app_date] => 2016-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2089
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198163
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/198163 | Method for the configuration of electronic devices, in particular for the configuration of components of an access control system | Jun 29, 2016 | Issued |
Array
(
[id] => 12875485
[patent_doc_number] => 20180183670
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => ENERGY MANAGEMENT IN A NETWORK
[patent_app_type] => utility
[patent_app_number] => 15/740502
[patent_app_country] => US
[patent_app_date] => 2016-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15514
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15740502
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/740502 | Energy management in a network | Jun 29, 2016 | Issued |