Search

Ji H. Bae

Examiner (ID: 19168, Phone: (571)272-7181 , Office: P/2115 )

Most Active Art Unit
2115
Art Unit(s)
2187, 2176, 2115, 2118
Total Applications
994
Issued Applications
781
Pending Applications
56
Abandoned Applications
167

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20731635 [patent_doc_number] => 12638893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Heterogeneous processor-based system for dynamically coupling power and clock to a last level cache [patent_app_type] => utility [patent_app_number] => 18/738175 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738175
Heterogeneous processor-based system for dynamically coupling power and clock to a last level cache Jun 9, 2024 Issued
Array ( [id] => 19466092 [patent_doc_number] => 20240319762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => METHODS AND APPARATUS FOR ORGANIZING A PROGRAMMABLE SEMICONDUCTOR DEVICE INTO MULTIPLE CLOCK REGIONS [patent_app_type] => utility [patent_app_number] => 18/731170 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731170
METHODS AND APPARATUS FOR ORGANIZING A PROGRAMMABLE SEMICONDUCTOR DEVICE INTO MULTIPLE CLOCK REGIONS May 30, 2024 Pending
Array ( [id] => 20528771 [patent_doc_number] => 12547206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Clock signal monitoring unit [patent_app_type] => utility [patent_app_number] => 18/640347 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640347
Clock signal monitoring unit Apr 18, 2024 Issued
Array ( [id] => 20530724 [patent_doc_number] => 12549168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Data transmission using delayed timing signals [patent_app_type] => utility [patent_app_number] => 18/638218 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15930 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638218 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638218
Data transmission using delayed timing signals Apr 16, 2024 Issued
Array ( [id] => 19530213 [patent_doc_number] => 20240354115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Electronic avionics system with additional configuration file [patent_app_type] => utility [patent_app_number] => 18/635325 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635325
Electronic avionics system with additional configuration file Apr 14, 2024 Issued
Array ( [id] => 20297238 [patent_doc_number] => 20250322481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO IDENTIFY PROCESSOR SETTINGS [patent_app_type] => utility [patent_app_number] => 18/632260 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 86015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632260
APPLICATION PROGRAMMING INTERFACE TO IDENTIFY PROCESSOR SETTINGS Apr 9, 2024 Pending
Array ( [id] => 19532819 [patent_doc_number] => 20240356721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR SAMPLING RECEIVED DATA [patent_app_type] => utility [patent_app_number] => 18/631133 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631133 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631133
Electronic device and method for sampling received data Apr 9, 2024 Issued
Array ( [id] => 20296366 [patent_doc_number] => 20250321609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO CONFIGURE A PROCESSOR USING COMPUTING RESOURCE INPUTS [patent_app_type] => utility [patent_app_number] => 18/632267 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 86156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632267
APPLICATION PROGRAMMING INTERFACE TO CONFIGURE A PROCESSOR USING COMPUTING RESOURCE INPUTS Apr 9, 2024 Pending
Array ( [id] => 20281423 [patent_doc_number] => 20250306665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => POWER MANAGEMENT ENGINE IN A SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/622533 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622533
POWER MANAGEMENT ENGINE IN A SEMICONDUCTOR SYSTEM Mar 28, 2024 Pending
Array ( [id] => 19320017 [patent_doc_number] => 20240241561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Power Management in Multi-Die SoCs through Hardware Power Control [patent_app_type] => utility [patent_app_number] => 18/622481 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622481
Power Management in Multi-Die SoCs through Hardware Power Control Mar 28, 2024 Pending
Array ( [id] => 20249580 [patent_doc_number] => 20250298449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO INDICATE POWER [patent_app_type] => utility [patent_app_number] => 18/615470 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615470
APPLICATION PROGRAMMING INTERFACE TO INDICATE POWER Mar 24, 2024 Pending
Array ( [id] => 19481676 [patent_doc_number] => 20240329718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => REDUCED POWER CONSUMPTION CIRCUIT AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 18/606928 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606928
REDUCED POWER CONSUMPTION CIRCUIT AND CORRESPONDING METHOD Mar 14, 2024 Abandoned
Array ( [id] => 20166481 [patent_doc_number] => 20250258528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => SYSTEMS, METHODS, AND DEVICES FOR DATA CENTER POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/436803 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436803
SYSTEMS, METHODS, AND DEVICES FOR DATA CENTER POWER MANAGEMENT Feb 7, 2024 Pending
Array ( [id] => 19654899 [patent_doc_number] => 12176706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Power management for network device line modules [patent_app_type] => utility [patent_app_number] => 18/433744 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6547 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433744
Power management for network device line modules Feb 5, 2024 Issued
Array ( [id] => 19382829 [patent_doc_number] => 20240272699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => POWER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/430932 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430932
POWER MANAGEMENT Feb 1, 2024 Pending
Array ( [id] => 20647290 [patent_doc_number] => 12602233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Boot program emulation method [patent_app_type] => utility [patent_app_number] => 18/430825 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430825
Boot program emulation method Feb 1, 2024 Issued
Array ( [id] => 20152348 [patent_doc_number] => 20250252186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => Runtime Trusted Execution Environment to Facilitate Information Handling System Firmware Management Operations [patent_app_type] => utility [patent_app_number] => 18/429603 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429603
Runtime Trusted Execution Environment to Facilitate Information Handling System Firmware Management Operations Jan 31, 2024 Pending
Array ( [id] => 20152103 [patent_doc_number] => 20250251941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => Adaptive Context Aware Information Handling System Stack Tuning [patent_app_type] => utility [patent_app_number] => 18/429579 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429579
Adaptive Context Aware Information Handling System Stack Tuning Jan 31, 2024 Pending
Array ( [id] => 20137971 [patent_doc_number] => 20250245015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => Processor Environment Architecture Agnostic Unified BIOS Memory Mapping Operation [patent_app_type] => utility [patent_app_number] => 18/429017 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429017 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429017
Processor environment architecture agnostic unified bios memory mapping operation Jan 30, 2024 Issued
Array ( [id] => 20481588 [patent_doc_number] => 12530063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Dynamic partitioning a power budget among compute agents of a system on chip (SoC) [patent_app_type] => utility [patent_app_number] => 18/415035 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415035
Dynamic partitioning a power budget among compute agents of a system on chip (SoC) Jan 16, 2024 Issued
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